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PDF FAN5234 Data sheet ( Hoja de datos )
| Número de pieza | FAN5234 | |
| Descripción | Mobile-Friendly PWM/PFM Controller | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FAN5234
Mobile-Friendly PWM/PFM Controller
www.fairchildsemi.com
Features
• Wide input voltage range (2 to 24V) for Mobile systems
• Excellent dynamic response with Voltage Feed-Forward
and Average Current Mode control
• Lossless current sensing on low-side MOSFET or
precision over-current using sense resistor
• VCC Under-voltage Lockout
• Power-Good Signal
• Light load Hysteretic mode maximizes efficiency
• QSOP16, TSSOP16
• 300Khz or 600Khz operation
Applications
• Mobile PC regulator
• Hand-Held PC power
General Description
The FAN5234 PWM controller provides high efficiency and
regulation with an adjustable output from 0.9V to 5.5V that
are required to power I/O, chip-sets, memory banks or
peripherals in high-performance notebook computers, PDAs
and Internet appliances. Synchronous rectification and
hysteretic operation at light loads contribute to a high
efficiency over a wide range of loads. The hysteretic mode of
operation can be disabled if PWM mode is desired for all
load levels. Efficiency is even further enhanced by using
MOSFET’s RDS(ON) as a current sense component.
Feed-forward ramp modulation, average current mode
control, and internal feedback compensation provide fast
response to load transients. The FAN5234 monitors these
outputs and generates a PGOOD (power good) signal when
the soft-start is completed and the output is within ±10% of
its set point. A built-in over-voltage protection prevents the
output voltage from going above 120% of the set point.
Normal operation is automatically restored when the over-
voltage conditions go away. Under-voltage protection latches
the chip off when the output drops below 75% of its set value
after the soft-start sequence is completed. An adjustable
over-current function monitors the output current by sensing
the voltage drop across the lower MOSFET.
Typical Application
VIN (BATTERY)
= 2 to 24V
+5 VCC 11
C4
R5 ILIM 4
C3
+5
R4
EN 3
SS1 7
FPWM 16
AGND 8
PGOOD 2
VIN
1
FAN5234
15 BOOT
Q1A
14 HDRV
13 SW
Q1B
10 LDRV
9 PGND
12 ISNS
6 VSEN
5 VOUT
C1 C2
D1
+5
C5
L1
R3
1.8V@ 3.5A
C6
R1
R2
Figure 1. 1.8V Output Regulator (see Table 2, page 12 for BOM)
REV. 1.0.8 1/10/03
1 page  
FAN5234
PRODUCT SPECIFICATION
EN
FPWM
SS
VIN
VSEN
POR/UVLO
HYST
OVP
OSC
CLK
RAMP
Q
SR
PWM
EA DUTY
CYCLE
CLAMP
5V
VDD
FPWM
HYST
ADAPTIVE
GATE
CONTROL LOGIC
VDD
RAMP
Σ
PWM
S/H
PWM/HYST
ILIM det. MODE
CURRENT PROCESSING
I
OU T
SS
PGOOD
REF2
Reference and
Soft Start
VREF
PWM/HYST
Figure 2. IC Block Diagram
ILIM
BOOT
C
BOOT
VIN
Q1
HDRV
SW
Q2
LDRV
PGND
VOUT
L OUT
COUT
ISNS RSENSE
Circuit Description
Overview
The FAN5234 is a PWM controller intended for low voltage
power applications in modern notebook, desktop, and
sub-notebook PCs. The output voltage of the controller can
be set in the range of 0.9V to 5.5V by an external resistor
divider.
The synchronous buck converter can operate from either an
unregulated DC source (such as a notebook battery) with
voltage ranging from 2V to 24V, or from a regulated system
rail. In either mode of operation the IC is biased from a +5V
source. The PWM modulator uses an average current mode
control with input voltage feed-forward for simplified feed-
back loop compensation and improved line regulation. The
controller includes integrated feedback loop compensation
that dramatically reduces the number of external compo-
nents.
Depending on the load level, the converter can operate either
in fixed frequency PWM mode or in a hysteretic mode.
Switch-over from PWM to hysteretic mode improves the
converters' efficiency at light loads and prolongs battery run
time. In hysteretic mode, a comparator is synchronized to the
main clock that allows seamless transition between the oper-
ational modes and reduced channel-to-channel interaction.
REV. 1.0.8 1/10/03
The hysteretic mode of operation can be inhibited indepen-
dently using the FPWM pin if variable frequency operation is
not desired.
Oscillator
Table 1. Converter Operating modes
Mode
Battery
Fixed
300
Fixed
600
FSW
(Khz)
300
300
600
Converter
Power
2 to 24V
< 5.5V Fixed
< 5.5V Fixed
VIN Pin
Battery (>5V)
100KΩ to GND
GND
When VIN is from the battery, the oscillator's ramp ampli-
tude is proportional to VIN, providing voltage feed-forward
control for improved loop response. When in either of the
Fixed modes, oscillator's ramp amplitude is fixed. The oper-
ating frequency is then determined according to the connec-
tion on the VIN pin (Table 1).
Initialization and Soft Start
Assuming EN is high, FAN5234 is initialized when VCC
exceeds the rising UVLO threshold. Should VCC drop below
the UVLO threshold, an internal Power-On Reset function
disables the chip.
5
5 Page 
FAN5234
PRODUCT SPECIFICATION
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1's switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
These losses are given by:
PUPPER = PSW + PCOND where:
PSW
=
-V----D----S----×-----I--L-
2
×
2
×
tS
FSW
(15a)
PCOND
=
V---V--O---I-U-N---T-
× IOUT2 × RDS(ON)
(15b)
PUPPER is the upper MOSFET's total losses, and PSW and
PCOND are the switching and conduction losses for a given
MOSFET. RDS(ON) is at the maximum junction temperature
(TJ). tS is the switching period (rise or fall time) and is t2+t3
(Figure 8).
The driver’s impedance and CISS determine t2 while t3’s
period is controlled by the driver's impedance and QGD.
Since most of tS occurs when VGS = VSP we can use a
constant current assumption for the driver to simplify the
calculation of tS:
VDS
C ISS
CRSS
CISS
tS
=
-Q-----G----(--S---W----)-
IDRIVER
≈
-----------------Q-----G----(--S---W----)-----------------
-R----D---R--V--I--VC----E-C--R---–-+----V-R---S--G-P--A----T---E--
(16)
Most MOSFET vendors specify QGD and QGS. QG(SW) can
be determined as: QG(SW) = QGD + QGS – QTH where QTH is
the gate charge required to get the MOSFET to it's threshold
(VTH). For the high-side MOSFET, VDS = VIN, which can
be as high as 20V in a typical portable application. Care
should also be taken to include the delivery of the
MOSFET's gate power (PGATE ) in calculating the power
dissipation required for the FAN5234:
PGATE = QG × VCC × FSW
(17)
where QG is the total gate charge to reach VCC.
Low-Side Losses
Q2, however, switches on or off with its parallel shottky
diode conducting, therefore VDS ≈ 0.5V. Since PSW is pro-
portional to VDS , Q2's switching losses are negligible and
we can select Q2 based on RDS(ON) only.
Conduction losses for Q2 are given by::
PCOND
=
(1
–
D)
×
IO
U
2
T
×
RDS(ON)
(18)
ID
VGS
VSP
VTH
QGS
QGD
QG(SW)
4.5V
t1
CISS = CGS || CGD
t2
t3 t4 t5
Figure 8. Switching losses and QG
5V
RD
HDRV
SW
C GD
RGATE
G
CGS
VIN
where RDS(ON) is the RDS(ON) of the MOSFET at the highest
operating junction temperature and
D
=
V-----O----U----T-
VIN
is the minimum duty cycle for the converter.
Since DMIN < 20% for portable computers, (1-D) ≈ 1
produces a conservative result, further simplifying the
calculation.
The maximum power dissipation (PD(MAX)) is a function of
the maximum allowable die temperature of the low-side
MOSFET, the θJ-A, and the maximum allowable ambient
temperature rise:
PD(MAX) = T----J---(-M-----A----X--θ-)---J–--–---T-A---A----(--M----A----X---)
(19)
θJ-A, depends primarily on the amount of PCB area that can
be devoted to heat sinking (see FSC app note AN-1029 for
SO-8 MOSFET thermal information).
Figure 9. Drive Equivalent Circuitt
REV. 1.0.8 1/10/03
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet FAN5234.PDF ] | |
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