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PDF FDN357N Data sheet ( Hoja de datos )
| Número de pieza | FDN357N | |
| Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
FDN357N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
SuperSOTTM-3 N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
1.9 A, 30 V, RDS(ON) = 0.090 Ω @ VGS = 4.5 V
RDS(ON) = 0.060 Ω @ VGS = 10 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
D
357
SuperSOT TM-3
G
S
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain/Output Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
D
GS
FDN357N
30
±20
1.9
10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
FDN357N Rev.C
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet FDN357N.PDF ] | |
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