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Fairchild Semiconductor - Dual P-Channel Logic Level PowerTrench MOSFET

Numéro de référence FDC6506
Description Dual P-Channel Logic Level PowerTrench MOSFET
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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FDC6506 fiche technique
February 1999
FDC6506P
Dual P-Channel Logic Level PowerTrenchMOSFET
General Description
Features
These P-Channel logic level MOSFETs are produced using
Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain low gate charge for
superior switching performance.
-1.8 A, -30 V. RDS(on) = 0.170 @ VGS = -10 V
RDS(on) = 0.280 @ VGS = -4.5 V
Low gate charge (2.3nC typical).
These devices have been designed to offer exceptional
power dissipation in a very small footprint for applications
where the bigger more expensive SO-8 and TSSOP-8
packages are impractical.
Applications
Load switch
Battery protection
Power management
Fast switching speed.
High performance trench technology for extremely
low RDS(ON).
SuperSOTTM-6 package: small footprint (72% smaller
than standard SO-8); low profile (1mm thick).
D2
S1
D1
SuperSOT TM-6
G2
S2
G1
43
52
61
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
PD
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, Tstg
Operating and Storage Junction Temperature Range
Ratings
-30
±20
-1.8
-10
0.96
0.9
0.7
-55 to +150
Units
V
V
A
W
°C
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Outlines and Ordering Information
Device Marking
Device
Reel Size
.506
FDC6506P
7’’
130
60
Tape Width
8mm
°C/W
°C/W
Quantity
3000 units
©1999 Fairchild Semiconductor Corporation
FDC6506P Rev. C

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