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PDF FDC6323L Data sheet ( Hoja de datos )
| Número de pieza | FDC6323L | |
| Descripción | Integrated Load Switch | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1999
FDC6323L
Integrated Load Switch
General Description
These Integrated Load Switches are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance and
provide superior switching performance. These
devices are particularly suited for low voltage high
side load switch application where low conduction loss
and ease of driving are needed.
Features
VDROP=0.2V @ VIN=5V, IL=1A, VON/OFF= 1.5V to 8V
VDROP=0.3V @ VIN=3.3V, IL=1A, VON/OFF= 1.5V to 8V.
High density cell design for extremely low on-resistance.
VON/OFF Zener protection for ESD ruggedness.
>6KV Human Body Model.
SuperSOTTM-6 package design using copper lead frame
for superior thermal and electrical capabilities.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
pin 1
SuperSOT TM-6
Vin,R1 4
O N / O FF 5
R1,C1 6
Q2
Q1
3 Vout,C1
2 Vout,C1
IN
EQUIVALENT CIRCUIT
+VDROP -
1 R2
O N / O FF
OUT
See Application Circuit
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VIN
VON/OFF
IL
Input Voltage Range
On/Off Voltage Range
Load Current @ VDROP=0.5V - Continuous (Note 1)
- Pulsed
(Note 1 & 3)
PD
TJ,TSTG
ESD
Maximum Power Dissipation
(Note 2a)
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D Human Body
Model (100pf/1500Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 2a)
RθJC Thermal Resistance, Junction-to-Case (Note 2)
© 1999 Fairchild Semiconductor Corporation
FDC6323L
3-8
1.5 - 8
1.5
2.5
0.7
-55 to 150
6
180
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6323L Rev.F
1 page  
Typical Electrical Characteristics (TA = 25 OC unless otherwise noted )
10
3
1
R(ON) LIMIT
0.3
0.1
0.03
0.01
0.1
VIN = 5V
SINGLE PULSE
RθJA = See Note 2a
TA = 25°C
0.2
0.5 1
2
VDROP (V)
100us
10m1ms s
100ms
1s
DC
5 10 20 30
Figure 12. Safe Operating Area.
1
0.5 D = 0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.00001
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.0001
0.001
0.01
0.1
t 1, TIME (sec)
RθJA (t) = r(t) * R θJA
R θJA = See Note 2a
P(pk)
t1
t2
TJ - TA = P * R θJA(t)
Duty Cycle, D = t 1/ t 2
1 10 100 300
Figure 13. Transient Thermal Response Curve.
Note: Thermal characterization performed on the conditions described in Note 2a.
Transient thermal response will change depends on the circuit board design.
FDC6323L Rev.F
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet FDC6323L.PDF ] | |
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