FM93CS46V Datasheet PDF - Fairchild Semiconductor
| Part Number | FM93CS46V | |
| Description | (MICROWIRE Bus Interface) 1024-Bit Serial EEPROM with Data Protect and Sequential Read | |
| Manufacturers | Fairchild Semiconductor | |
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July 2000
FM93CS46
(MICROWIRE™ Bus Interface) 1024-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
FM93CS46 is a 1024-bit CMOS non-volatile EEPROM organized
as 64 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
FM93CS46 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS46, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconduc-
tor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
“LZ” and “L” versions of FM93CS46 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Features
I Wide VCC 2.7V - 5.5V
I Programmable write protection
I Sequential register read
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
ADDRESS
REGISTER
PROTECT
REGISTER
COMPARATOR
AND
WRITE ENABLE
VCC
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
DATA IN/OUT REGISTER
16 BITS
DO DATA OUT BUFFER
VSS
© 2000 Fairchild Semiconductor International
FM93CS46 Rev. C.1
1
www.fairchildsemi.com
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Pin Description
Chip Select (CS)
This is an active high input pin to FM93CS46 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
TABLE 1. Instruction set
Program Enable (PE)
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on FM93CS46. The format of each instruction is
listed in Table 1.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Start Bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
Address Field
This is a 6-bit field and should immediately follow the Opcode bits.
In FM93CS46, all 6 bits are used for address decoding during
READ, WRITE and PRWRITE instructions. During all other in-
structions (with the exception of PRREAD), the MSB 2 bits are
used to decode instruction (along with Opcode bits, PRE and PE
signals).
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
Instruction
READ
WEN
WRITE
WRALL
WDS
PRREAD
PREN
PRCLEAR
PRWRITE
PRDS
Start Bit
1
1
1
1
1
1
1
1
1
1
Opcode Field
Address Field
Data Field PRE Pin
10 A5 A4 A3 A2 A1 A0
0
00 1 1 X X X X
0
01 A5 A4 A3 A2 A1 A0 D15-D0
0
00 0 1 X X X X D15-D0 0
00 0 0 X X X X
0
10 X X X X X X
1
00 1 1 X X X X
1
11 1 1 1 1 1 1
1
01 A5 A4 A3 A2 A1 A0
1
00 0 0 0 0 0 0
1
PE Pin
X
1
1
1
X
X
1
1
1
1
FM93CS46 Rev. C.1
5 www.fairchildsemi.com
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FM93CS46V electronic component. |
| Information | Total 16 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FM93CS46V.PDF Datasheet ] | |
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