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PDF FM3808 Data sheet ( Hoja de datos )
| Número de pieza | FM3808 | |
| Descripción | 256Kb Bytewide FRAM w/ Real-Time Clock | |
| Fabricantes | ETC | |
| Logotipo |  |
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Preliminary
FM3808
256Kb Bytewide FRAM w/ Real-Time Clock
Features
256K bit Ferroelectric Nonvolatile RAM
• Organized as 32,752 x 8 bits
• High Endurance 100 Billion (1011) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• 70 ns Access Time/ 130 ns Cycle Time
• Built-in Low VDD Protection
Real-Time Clock/Calendar Function
• Clock Registers in Top 16 bytes of Address Space
• Backup Power from External Capacitor or Battery
• Tracks Seconds through Centuries in BCD Format
• Tracks Leap Years through 2099
• Runs from a 32.768 kHz Timekeeping Crystal
System Supervisor Function
• Programmable Clock/Calendar Alarm
• Programmable Watchdog Timer
• Power Supply Monitor
• Interrupt Output - Programmable active high/low
• Control Settings Inherently Nonvolatile
• Generates either Processor Reset or Interrupt
Low Power Operation
• 5V Operation for Memory and Clock Interface
• Backup Voltage as low as 2.5V
• 25 mA IDD Active Current
• 1 µA IBAK Clock Backup Current
Description
The FM3808 combines a 256Kb FRAM array with a
real-time clock and a system supervisor function. An
external 32.768 kHz crystal drives the timekeeping
function. It maintains time and date settings in the
absence of system power through the user’s choice of
backup power source – either a capacitor or a battery.
In either case data in the memory array does not
depend on the backup source, it remains nonvolatile
in FRAM. In addition to timekeeping, the FM3808
includes a system supervisor to manage low VDD
power conditions and a watchdog timer function. A
programmable interrupt output pin allows the user to
select the supervisor functions and the polarity of the
signal.
Pin Configuration
A11
A9
A8
A13
WE
VBAK
INT
VDD
X1
X2
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
Both the FRAM array and the timekeeping function
are accessed through the memory interface. The
upper 16-address locations of the memory space are
allocated to the timekeeping registers rather than to
memory. The FRAM array provides data retention
for 10 years in the absence of system power, and is
not dependent on the backup power source for the
clock. This eliminates system concerns over data loss
in a traditional battery-backed RAM solution. In
addition, clock and supervisor control settings are
implemented in FRAM rather than battery-backed
RAM, making them more dependable. The FM3808
offers guaranteed operation over an industrial
temperature range of -40°C to +85°C.
Ordering Information
FM3808-70-T 70 ns access, 32-pin TSOP
FM3808DK
DIP module development kit
Documentation for the DIP module development kit is
available separately.
This is a product in sampling or pre-production phase of develop-
ment. Characteristic data and other specifications are subject to
change without notice.
Rev 1.1
May 2003
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, FAX (719) 481-7058
www.ramtron.com
Page 1 of 28
1 page  
Address
7FF8h
/OSCEN
Reserved
CALS
CAL.3-0
7FF7h
WDS
/WDW
WDT.5-0
7FF6h
WIE
AIE
PFE
ABE
H/L
P/L
7FF5h
/M
FM3808
Description
Control-Nonvolatile
D7 D6 D5 D4 D3 D2 D1
D0
OSCEN Reserved Reserved
CALS
CAL.3
CAL.2
CAL.1
CAL.0
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling
the oscillator saves battery power during storage. On a no-battery power up, this bit is set to 1. The
RTC will not run until the oscillator is enabled. Set this bit to 0 to activate the RTC.
Do not use. Should remain set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base. This bit is implemented in FRAM. Calibration is explained below
These four bits control the calibration of the clock. These bits are implemented in FRAM.
Watchdog Timer
D7 D6 D5 D4 D3 D2 D1
D0
WDS
WDW
WDT.5
WDT.4
WDT.3
WDT.2
WDT.1
WDT.0
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no
affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only.
Reading it always will return a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT.5-0) so it cannot
be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this
bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register. The new value will be
loaded on the next internal watchdog clock after the write cycle is complete. This function is explained
in more detail in the watchdog Timer section below.
Watchdog Timeout selection. The watchdog timer interval is selected by the 6-bit value in this register.
It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25
ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh). Setting the watchdog timer
register to 0 disables the timer. These bits can be written only if the /WDW bit was cleared to 0 on a
previous cycle.
Interrupts
D7 D6 D5 D4 D3 D2 D1
D0
WIE AIE
PFE ABE H/L
P/L
Reserved
Reserved
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives
the INT pin as well as the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the power-fail monitor drives the pin as well as the PF flag. When set
to 0, the power-fail monitor affects only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when VDD>VLO.
High/Low. When set to a 1, the INT pin is push/pull active high. When set to a 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until
the Flags/Control register is read.
Alarm – Date of the month
D7 D6 D5 D4 D3 D2 D1
D0
M
0
10 date.1 10 date.0
Date.3
Date.2
Date.1
Date.0
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
Rev 1.1
May 2003
Page 5 of 28
5 Page 
Watchdog Timer
The Watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The oscillator must be running
(/OSCEN=0) for the watchdog to function. It begins
counting down from the value loaded in the
Watchdog Timer register (7FF7h).
The counter consists of a loadable register and a free
running counter. On power up, the watchdog timeout
value in 7FF7h is loaded into the counter load
register. Counting begins on power up and restarts
from the loadable value any time the Watchdog
Strobe WDS bit (7FF7h bit D7) is set to 1. The
counter is compared to terminal value of 0. If the
counter reaches this value, it causes an internal flag
and an optional interrupt output (see interrupts
below). The user can prevent the timeout interrupt by
setting WDS bit to 1 prior to the counter reaching 0.
This causes the counter to be reloaded with the
watchdog timeout value and to be restarted. As long
as the user sets the WDS bit prior to the counter
reaching the terminal value, the interrupt and flag
never occurs.
FM3808
New timeout values can be written by setting the
watchdog write bit (7FF7h bit D6) to 0. When the
/WDW bit is 0 (from a previous operation), new
writes to the watchdog timeout value 7FF7h bits D5-
D0 allow the timeout value to be modified. When
/WDW is a 1, then writes to bits 7FF7h bits D4-D0
will be ignored. The /WDW function allows a user to
set the WDS bit without concern that the watchdog
timer value will be modified. A logical diagram of the
watchdog timer is shown below. Note that setting the
watchdog timeout value to 0 would be otherwise
meaningless and therefore disables the watchdog
function.
The output of the watchdog timer is a flag bit WDF
(7FF0h bit D7) that is set if the watchdog is allowed
to timeout. The flag is set upon a watchdog timeout
and cleared when the Flags/Control register is read by
the user. The user can also enable an optional
interrupt source to drive the INT pin if the watchdog
timeout occurs. The interrupt function is described on
page 13.
Oscillator
32.768 kHz
Clock
Divider
1 Hz
32 Hz
Counter
Zero
Compare
WDS
Load Register
WDW
DQ
Q
write to
Watchdog
register
7FF7.5-0
Watchdog
register
Figure 3. Watchdog Timer Block Diagram
7FF0.7
WDF
Rev 1.1
May 2003
Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet FM3808.PDF ] | |
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