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PDF FM30C256-S Data sheet ( Hoja de datos )
| Número de pieza | FM30C256-S | |
| Descripción | 256Kb Data Collector | |
| Fabricantes | ETC | |
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FM30C256
256Kb Data Collector
Features
256K bit Ferroelectric Nonvolatile RAM
• Organized as 32,768 x 8 bits
• High Endurance 10 Billion (1010) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1 MHz Maximum Bus Frequency
• Supports Legacy Timing for 100 kHz & 400 kHz
• Clock Registers Accessed via 2-wire Interface
Description
The FM30C256 is a 256-kilobit data collection
subsystem including nonvolatile RAM, timekeeping,
CPU supervisor, and system tamper detection. Non-
volatile RAM is provided by FRAM technology,
which is ideal for collection data and requires no
battery backup for nonvolatile storage. In other
respects, it provides the same features as SRAM.
FRAM performs write operations at bus speed with
no write delays. Write cycles can be continuous
without block limitations. In addition, it offers much
higher write endurance than other nonvolatile
memories. The FM30C256 supports up to 1010
read/write cycles.
The FM30C256 also includes timekeeping with
external battery backup. The timekeeper consists of
registers that represent time and date information in
BCD format. The clock includes a calibration mode
that allows a software adjustment for timekeeping
accuracy.
To maintain system data integrity, the FM30C256
provides a reset signal asserted when VDD is out of
tolerance. /RST remains active for 100 ms after VDD
returns to proper levels. The FM30C256 also
provides a battery-backed tamper detect circuit that
records a rising edge on the TIN input. A battery-
backed flag is set when the event occurs, but can only
be cleared by software.
The FM30C256 is provided in a 20-pin SOIC
package and is guaranteed over an industrial
temperature range of –40°C to +85°C.
Real-time Clock/Calendar
• Backup Current under 1 µA
• Tracks Seconds through Centuries (BCD format)
• Tracks Leap Years through 2099
• Uses Standard 32.768 kHz Crystal (6pF)
• Software Calibration
System Supervisor
• Active-low Reset Output for VDD Out-of-Tolerance
• Tamper Detect Input with Battery Backup and
Time Stamp
Pin Configuration
TIN
A0
A1
A2
NC
NC
NC
CAL
RST
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
SCL
SDA
NC
NC
NC
NC
X2
X1
VBAK
Pin Names
TIN
A0-A2
CAL
/RST
X1, X2
SDA
SCL
VDD
VBAK
VSS
Function
Tamper Detect input
Device Select inputs
Clock Calibration output
Reset Output
Crystal Connections
Serial Data
Serial Clock
Supply Voltage 5V
Battery-Backup input
Ground
Ordering Information
FM30C256-S 20-pin SOIC
This product conforms to specifications per the terms of the Ramtron
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.
Rev 2.1
Dec. 2002
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
Page 1 of 18
1 page  
Address
1h
/OSCEN
TSEN
CALS
CAL.4-0
0h
Tamper
CF
TST
CAL
W
R
Reserved
FM30C256
Description
CAL/Control
D7 D6 D5 D4 D3 D2 D1
D0
OSCEN
TSEN
CALS
CAL.4
CAL.3
CAL.2
CAL.1
CAL.0
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling
the oscillator can save battery power during storage. On a power-up without battery, this bit is set to 1.
Time Stamp Enable. When set to 1, a Tamper Detect event will record the date and time of the event.
On a power-up without battery, this bit is set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base. Calibration is explained below.
These five bits control the calibration of the clock.
Flags/Control
D7 D6 D5 D4 D3 D2 D1
D0
Tamper
CF
Reserved Reserved
TST
CAL
W
R
Tamper Detect. This bit is set to 1 when rising edge is detected on the TIN pin. It can only be cleared to
0 by the user.
Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to
00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should
record the new century information as needed. This bit is cleared to 0 when the Flag register is read. It is
read-only for the user.
Invokes factory test mode. Users should always set this bit to 0.
Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock
operates normally, and the CAL pin is driven low.
Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write
them with updated values. Setting the W bit to 0 causes the contents of the time registers to be
transferred to the timekeeping counters.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a
holding register. The user can then read them without concerns over changing values causing system
errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior
to reading again.
Reserved bits. Do not use. Should remain set to 0.
Real-time Clock Operation
The real-time clock (RTC) consists of an oscillator,
divider, and a register system for accessing the
information. It divides down the 32.768 kHz time-
base and provides a minimum resolution of seconds
(1Hz) to the user. Static registers provide the user
with read/write access to the time values. The
synchronization of these registers with the
timekeeper core is performed using R and W bits in
register 0.
Changing the R bit from 0 to 1 causes a transfer of
the timekeeping information to holding registers that
can be read by the user. If a timekeeper update is
pending when R is set, then the update will be
completed prior to loading the registers. Another
update cannot be performed until the R bit is cleared
to 0.
Setting the W bit to 1 causes the timekeeper to freeze
updates. Clearing it to 0 causes the values in the time
Rev 2.1
Dec. 2002
registers to be written into the timekeeper core. Users
should be certain not to load invalid values, such as
FFh, to the timekeeping registers.
Updates to the timekeeping core occur continuously
except when frozen. A diagram of the timekeeping
core follows.
Backup Power
The real-time clock/calendar is intended for
permanently powered operation. When the primary
system power fails, the voltage on the VDD pin will
drop. When VDD is less than the voltage on the
VBAK pin, the clock will switch to the backup power
supply. The clock operates at extremely low current
in order to maximize battery life. However, an
advantage of combining a clock function with FRAM
is that the 256K memory data is not lost regardless of
the backup power source.
Page 5 of 18
5 Page 
be complete before the Acknowledge is sent.
Therefore, if the user desires to abort a write without
altering the memory contents, this should be done
FM30C256
using a Start or Stop condition prior to the 8th data
bit. Figures 6 and 7 illustrate a single- and multiple-
writes to memory.
By Master
Start
Address & Data
S Slave Address 0 A
Address MSB A
Address LSB
A
By FM30C256
Acknowledge
Figure 6. Single Byte Memory Write
Start
By Master
Address & Data
S Slave Address 0 A
Address MSB
A
Address LSB
By FM30C256
Acknowledge
A
Data Byte
Figure 7. Multiple Byte Memory Write
Stop
Data Byte
AP
Stop
A Data Byte A P
Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM30C256 uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM30C256 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the
FM30C256 will begin shifting data out from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Rev 2.1
Dec. 2002
Each time the bus master acknowledges a byte,
this indicates that the FM30C256 should read
out the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM30C256 attempts to
read out additional data onto the bus. The four valid
methods follow.
1. The bus master issues a No-Acknowledge in the
9th clock cycle and a Stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
2. The bus master issues a No-Acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a Stop in the 9th clock
cycle.
4. The bus master issues a Start in the 9th clock
cycle.
If the internal address reaches 7FFFh, it will wrap
around to 0000h on the next read cycle. Figures 8 and
9 show the proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
Page 11 of 18
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| PDF Descargar | [ Datasheet FM30C256-S.PDF ] | |
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