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PDF FM25640 Data sheet ( Hoja de datos )
| Número de pieza | FM25640 | |
| Descripción | 64Kb FRAM Serial Memory | |
| Fabricantes | ETC | |
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FM25640
64Kb FRAM Serial Memory
Features
64K bit Ferroelectric Nonvolatile RAM
• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced high-reliability ferroelectric process
Very Fast Serial Peripheral Interface - SPI
• Up to 5 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Description
The FM25640 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
Unlike serial EEPROMs, the FM25640 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array mere
hundreds of nanoseconds after it has been
successfully transferred to the device. The next bus
cycle may commence immediately. In addition, the
product offers substantial write endurance compared
with other nonvolatile memories. The FM25640 is
capable of supporting up to 1012-read/write cycles --
far more than most systems will require from a serial
memory.
These capabilities make the FM25640 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25640 provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25640 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. The specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• 10 µA Standby Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
Pin Names
/CS
/HOLD
/WP
SCK
SI
SO
VDD
VSS
Function
Chip Select
Hold
Write Protect
Serial Clock
Serial Data Input
Serial Data Output
5V
Ground
Ordering Information
FM25640-S
8-pin SOIC
This product conforms to specifications per the terms of the Ramtron
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.
Rev. 2.1
Aug. 2003
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
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1 page  
Ramtron
Data Transfer
All data transfers to and from the FM25640 occur in
8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. Serial inputs are clocked in on the rising
edge of SCK. Outputs are driven on the falling edge
of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25640. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register. Last are
commands for memory transactions followed by
address and one or more bytes of data.
Table 1. Op-code Commands
Name Description
WREN Set Write Enable Latch
WRDI Write Disable
RDSR Read Status Register
WRSR Write Status Register
READ Read Memory Data
WRITE Write Memory Data
Op-code value
00000110b
00000100b
00000101b
00000001b
00000011b
00000010b
FM25640
WREN - Set Write Enable Latch
The FM25640 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 4 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
5 below illustrates the WRDI command bus
configuration.
Figure 5. WREN Bus Configuration
Rev. 2.1
Aug 2003
Figure 6. WRDI Bus Configuration
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5 Page 
AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
Min Max
fCK SCK Clock Frequency
0 5.0
tCH Clock High Time
90
tCL Clock Low Time
90
tCSU
Chip Select Setup
90
tCSH
Chip Select Hold
90
tOD Output Disable
100
tODV
Output Data Valid
60
tOH Output Hold
0
tD Deselect Time
100
tR Data In Rise Time
1
tF Data In Fall Time
1
tH Data Hold Time
30
tSU Data Setup Time
20
tHS /Hold Setup Time
70
tHH /Hold Hold Time
40
tHZ /Hold Low to Hi-Z
100
tLZ /Hold High to Data Active
50
Notes
1. Rise and fall times measured between 10% and 90% of waveform.
2. Characterized but not 100% tested in production.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
Capacitance TA = 25° C, f=1.0 MHz, VDD = 5V
Symbol Parameter
CO Output capacitance (SDA)
CI Input capacitance
Max
8
6
Notes
1. This parameter is periodically sampled and not 100% tested.
Units
pF
pF
Notes
1
1
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
10% and 90% of VDD
10 ns
VDD*0.5
Equivalent AC Load Circuit
FM25640
Notes
2
1,2
1,2
2
2
Data Retention VDD = 4.5V to 5.5V unless otherwise specified
Parameter
Min Units
Data Retention
10 Years
Notes
Rev. 2.1
Aug 2003
11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet FM25640.PDF ] | |
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