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PDF FM24CL64-S Data sheet ( Hoja de datos )
| Número de pieza | FM24CL64-S | |
| Descripción | 64Kb 2.7V-3.6V FRAM Serial Memory | |
| Fabricantes | ETC | |
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Preliminary
FM24CL64
64Kb 2.7V-3.6V FRAM Serial Memory
Features
64K bit Ferroelectric Nonvolatile RAM
• Organized as 8,192 x 8 bits
• Unlimited read/write cycles
• 10 year data retention at 85° C
• NoDelay™ write
• Advanced high-reliability ferroelectric process
Fast Two-wire Serial Interface
• Up to 1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz
Description
The FM24CL64 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
The FM24CL64 performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array mere hundreds of nanoseconds
after it has been successfully transferred to the
device. The next bus cycle may commence
immediately. Fast-write time and unlimited
read/write endurance make it superior to other types
of nonvolatile memory and a good substitute for
ordinary SRAM
These capabilities make the FM24CL64 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24CL64 provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The FM24CL64 is
provided in industry standard 8-pin surface mount
package using a familiar two-wire protocol. It is
guaranteed over an industrial temperature range of
-40°C to +85°C.
Low Power Operation
• True 2.7V-3.6V operation
• 75 µA Active current (100 kHz)
• 1 µA Standby current
Industry Standard Configuration
• Industrial temperature -40° C to +85° C
• 8-pin SOP
Pin Configuration
A0
A1
A2
VSS
VDD
WP
SCL
SDA
Pin Names
A0-A2
SDA
SCL
WP
VSS
VDD
Function
Device Select Address
Serial Data/address
Serial Clock
Write Protect
Ground
Supply Voltage
Ordering Information
FM24CL64-S 8-pin SOP
This data sheet contains specifications for a product under development.
Characterization is not complete; the specifications may change without notice.
9 May 2001
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
1/1
1 page  
Ramtron
Figure 4. Slave Address
Slave
ID
Dev ice
Select
1 0 1 0 A2 A1 A0 R/W
7 6 5 43 2 1 0
Addressing Overview
After the FM24CL64 (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB. Since the
device uses only 13 address bits, the value of the
upper three bits are don’t care. Following the MSB is
the LSB with the remaining eight address bits. The
address value is latched internally. Each access
causes the latched address value to be incremented
automatically. The current address is the value that is
held in the latch -- either a newly written value or the
address following the last access. The current address
will be held for as long as power remains or until a
new value is written. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24CL64 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (1FFFh) is reached, the address latch will
roll over to 0000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24CL64 can begin. For a read operation the
FM24CL64 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24CL64 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24CL64 will end the read operation. For a
write operation, the FM24CL64 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs msb (most significant bit) first.
FM24CL64
Memory Operation
The FM24CL64 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL64 and a similar
configuration EEPROM during writes. The
complete operation for both writes and reads is
explained below.
Write Operation
All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the lsb of the device address to
a 0. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies,
there is no effective write delay with FRAM. Since
the read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ready condition.
Internally, an actual memory write occurs after the
8th data bit is transferred. It will be complete before
the acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using start or stop
condition prior to the 8th data bit. The FM24CL64
uses no page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL64 will not acknowledge data bytes that are
written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figure 5 below illustrates both a single-byte and
multiple-write.
9 May 2001
5/5
5 Page 
Ramtron
8-pin SOP JEDEC MS-012
FM24CL64
Index
Area
EH
Pin 1
D
B
e
A
A1
h
α
.10 mm
.004 in.
45 °
L
C
Selected Dimensions
Refer to JEDEC MS-012 for complete dimensions and
notes.
Controlling dimensions is in millimeters. Conversions to
inches are not exact.
Symbol
A
A1
B
C
D
E
e
H
h
L
α
Dim
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
Min
1.35
.053
.10
.004
.33
.013
.19
.007
4.80
.189
3.80
.150
5.80
.228
.25
.010
.40
.016
0°
Nom.
1.27 BSC
.050 BSC
Max
1.75
.069
.25
.010
.51
.020
.25
.010
5.00
.197
4.00
.157
6.20
.244
.50
.197
1.27
.050
8°
9 May 2001
11/11
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