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PDF FM24CL16-S Data sheet ( Hoja de datos )
| Número de pieza | FM24CL16-S | |
| Descripción | 16Kb FRAM Serial 3V Memory | |
| Fabricantes | ETC | |
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FM24CL16
16Kb FRAM Serial 3V Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• Unlimited Read/Write Cycles
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
• Up to 1MHz maximum bus frequency
• Direct hardware replacement for EEPROM
Description
The FM24CL16 is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for over 10
years while eliminating the complexities, overhead,
and system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM24CL16 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. In
addition, the product offers unlimited write
endurance, orders of magnitude more endurance than
EEPROM. Also, FRAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24CL16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where a long write time
can cause data loss. The combination of features
allows the system to write data more frequently, with
less system overhead.
The FM24CL16 is available in an industry standard
8-pin SOIC and uses a two-wire protocol. The
specifications are guaranteed over the industrial
temperature range from -40°C to +85°C. Although
the FM24CL16 is functionally compatible with the
5V FM24C16, it offers 3V operation and up to 1MHz
bus speed.
Low Power Operation
• New 2.7 - 3.6V operation
• 75 µA Active Current (100 kHz) @ 3V
• 1 µA Standby Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC
• New “Green” 8-pin SOIC Package
Pin Configuration
NC 1 8
NC 2 7
NC 3 6
VSS 4 5
VDD
WP
SCL
SDA
Pin Names
SDA
SCL
WP
VDD
VSS
Function
Serial Data/Address
Serial Clock
Write Protect
Supply Voltage
Ground
Ordering Information
FM24CL16-S 8-pin SOIC
FM24CL16-G 8-pin SOIC - “Green” Assembly
Flow
This product conforms to specifications per the terms of the Ramtron
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.
Rev. 2.2
July 2003
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
Page 1 of 13
1 page  
Slave ID
Page
Select
1 0 1 0 A2 A1 A0 R/W
Figure 4. Slave Address
Word Address
After the FM24CL16 (as receiver) acknowledges the
slave ID, the master will place the word address on
the bus for a write operation. The word address is the
lower 8-bits of the address to be combined with the 3-
bits of the page select to specify the exact byte to be
written. The complete 11-bit address is latched
internally.
No word address occurs for a read operation, though
the 3-bit page select is latched internally. Reads
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the
address following the previous access. A random read
address can be loaded by doing a write operation as
explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24CL16 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (7FFh) is reached, the address latch will
roll over to 000h. There is no limit on the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24CL16 can begin. For a read operation the
device will place 8 data bits on the bus then wait for
an acknowledge. If the acknowledge occurs, the next
sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24CL16 will
accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
FM24CL16
Memory Operation
The FM24CL16 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL16 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave ID then a word address
as previously mentioned. The bus master indicates a
write operation by setting the LSB of the Slave
Address to a 0. After addressing, the bus master
sends each byte of data to the memory and the
memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
end of the address range is reached internally, the
address counter will wrap from 7FFh to 000h.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ‘ready’ condition.
An actual memory array write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition
prior to the 8th data bit. The FM24CL16 needs no
page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL16 will not acknowledge data bytes that are
written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.
Rev 2.2
July 2003
Page 5 of 13
5 Page 
FM24CL16
Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.
Read Bus Timing
SCL
SDA
tSU:SDA
tR
tBUF
tHIGH
tF
Start
Stop Start
1/fSCL
tAA
tLOW
tDH
tSP
tHD:DAT
tSU:D AT
Acknowledge
tSP
Write Bus Timing
SCL
SDA
tSU:STO
t
HD:STA
tHD:DAT
tSU:DAT
Start
Stop Start
tAA
Acknowledge
Data Retention (VDD = 2.7V to 3.65V unless otherwise specified)
Parameter
Min Units
Data Retention
10 Years
Notes
Rev 2.2
July 2003
Page 11 of 13
11 Page | ||
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| PDF Descargar | [ Datasheet FM24CL16-S.PDF ] | |
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