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PDF 100355QI Data sheet ( Hoja de datos )
| Número de pieza | 100355QI | |
| Descripción | Low Power Quad Multiplexer/Latch | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 1989
Revised August 2000
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of
which can accept and store data from two sources. When
both Enable (En) inputs are LOW, the data that appears at
an output is controlled by the Select (Sn) inputs, as shown
in the Operating Mode table. In addition to routing data
from either D0 or D1, the Select inputs can force the out-
puts LOW for the case where the latch is transparent (both
Enables are LOW) and can steer a HIGH signal from either
D0 or D1 to an output. The Select inputs can be tied
together for applications requiring only that data be steered
from either D0 or D1. A positive-going signal on either
Enable input latches the outputs. A HIGH signal on the
Master Reset (MR) input overrides all the other inputs and
forces the Q outputs LOW. All inputs have 50 kΩ pull-down
resistors.
Features
s Greater than 40% power reduction of the 100155
s 2000V ESD protection
s Pin/function compatible with 100155
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100355PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100355QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100355QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
Description
E1, E2
S0, S1
MR
Dna–Dnd
Qa–Qd
Qa–Qd
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010147
28-Pin PLCC
www.fairchildsemi.com
1 page  
Commercial Version (Continued)
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
tPLH Propagation Delay
tPHL
Dna–Dnd to Output
(Transparent Mode)
tPLH Propagation Delay
tPHL S0, S1 to Output
(Transparent Mode)
tPLH Propagation Delay
tPHL E1, E2 to Output
tPLH Propagation Delay
tPHL MR to Output
tTLH Transition Time
tTHL 20% to 80%, 80% to 20%
tS Setup Time
Dna–Dnd
S0, S1
MR (Release Time)
tH Hold Time
Dna–Dnd
S0, S1
TC = 0°C
Min Max
0.60
1.70
1.00
2.40
0.80
0.80
0.60
1.80
2.10
1.30
0.80
1.60
1.40
0.30
−0.10
TC = +25°C
Min Max
0.60
1.70
1.00
2.40
0.80
0.80
0.60
1.80
2.10
1.30
0.80
1.60
1.40
0.30
−0.10
TC = +85°C
Min Max
0.70
1.80
1.20
2.50
0.80
0.80
0.60
1.90
2.10
1.30
0.80
1.60
1.40
0.30
−0.10
Units
Conditions
ns
Figures 1, 2
ns
ns
ns Figures 1, 3
ns Figures 1, 2
ns Figure 4
Figure 3
ns Figure 4
tPW (L)
tPW (H)
tOSHL
tOSLH
tOST
tPS
Pulse Width LOW E1, E2
Pulse Width HIGH MR
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
Maximum Skew Opposite Edge
Output-to-Output Variation
Data to Output Path
Maximum Skew
Pin (Signal) Transition Variation
Data to Output Path
2.00
2.00
2.00
2.00
2.00
2.00
330 330 330
370 370 370
370 370 370
270 270 270
ns Figure 2
ns Figure 3
PLCC only
ps (Note 5)
PLCC only
ps (Note 5)
PLCC only
ps (Note 5)
PLCC only
ps (Note 5)
Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 100355QI.PDF ] | |
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