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PDF M24256 Data sheet ( Hoja de datos )
| Número de pieza | M24256 | |
| Descripción | 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M24256
M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
PRELIMINARY DATA
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage:
– 4.5V to 5.5V for M24xxx
– 2.5V to 5.5V for M24xxx-W
s Hardware Write Control
s BYTE and PAGE WRITE (up to 64 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s 100,000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
The M24256 and M24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
Table 1. Signal Names
SDA
Serial Data/Address Input/
Output
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
SCL SDA
M24256
M24128
WC
SCL
WC
VCC
VSS
Serial Clock
Write Control
Supply Voltage
Ground
VSS
AI01882
November 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/16
1 page  
M24256, M24128
Table 4. Operating Modes
Mode
RW bit
Current Address Read
1
Random Address Read
0
1
Sequential Read
1
Byte Write
0
Page Write
Note: 1. X = VIH or VIL.
0
WC 1
X
X
X
X
VIL
VIL
Data Bytes
Initial Sequence
1 START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
1
reSTART, Device Select, RW = ‘1’
≥ 1 Similar to Current or Random Address Read
1 START, Device Select, RW = ‘0’
≤ 64 START, Device Select, RW = ‘0’
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
BYTE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01120B
5/16
5 Page 
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
SDA IN
tCHDX
tCLDX
START
CONDITION
SDA
SDA
INPUT CHANGE
SCL
SDA OUT
tCLQV
DATA VALID
tCLQX
DATA OUTPUT
M24256, M24128
tCHDH
tDHDL
STOP &
BUS FREE
SCL
SDA IN
tCHDH
STOP
CONDITION
tW
WRITE CYCLE
tCHDX
START
CONDITION
AI00795B
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet M24256.PDF ] | |
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