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M2021 Datasheet دیتاشیت PDF دانلود

دیتاشیت - Integrated Circuit Systems - VCSO BASED CLOCK PLL

شماره قطعه M2021
شرح مفصل VCSO BASED CLOCK PLL
تولید کننده Integrated Circuit Systems 
آرم Integrated Circuit Systems 


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M2021 شرح
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2020/21
VCSO BASED CLOCK PLL
GENERAL DESCRIPTION
The M2020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M2020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
Output frequencies of 15 to 700 MHz *
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW pin)
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available for SONET (GR-253) /
SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
Industrial temperature grade available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M2020
32 M 2 0 2 1
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2020-11-622.0800 or M2021-11-622.0800
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(M2020)
(M2021)
19.44 or 38.88
(M2020) (M2021)
32 or 16
77.76
155.52
8 622.08
4
622.08
1
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
LOL
M2020/21
Loop
Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL1:0 2
FIN_SEL1:0 2
P_SEL2:0 3
MUX
0 R Div
(1, 4,
16, 64)
1
Phase
Detector
VCSO
M / R Divider
LUT
M Divider
(1, 4, 16, 64)
Mfin Div
(1, 4, 8, 32) or
( 1, 4, 8, 16)
Mfin Divider
LUT
P Divider
TriState
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
P Divider
LUT
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 2: Simplified Block Diagram
M2020/21 Datasheet Rev 1.0
Revised 30Jul2004
M2020/21 VCSO Based Clock PLL
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

قانون اساسیصفحه 10
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