PDF M14C16 Data sheet ( Hoja de datos )

Número de pieza	M14C16
Descripción	Memory Micromodules General Information for D1/ D2 and C Packaging
Fabricantes	STMicroelectronics
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No Preview Available ! M14C16 M14C04 Memory Card IC 16/4 Kbit Serial I²C Bus EEPROM s Two Wire I2C Serial Interface Supports 400 kHz Protocol s Single Supply Voltage (2.5 V to 5.5 V) s Hardware Write Control s BYTE and PAGE WRITE (up to 16 Bytes) s BYTE, RANDOM and SEQUENTIAL READ Modes s Self-Timed Programming Cycle s Automatic Address Incrementing s Enhanced ESD/Latch-Up Behaviour s 1 Million Erase/Write Cycles (minimum) s 40 Year Data Retention (minimum) s 5 ms Programming Time (typical) DESCRIPTION Each device is an electrically erasable program- mable memory (EEPROM) fabricated with STMi- croelectronics’s High Endurance, Single Polysilicon, CMOS technology. This guarantees an endurance typically well above one million Erase/Write cycles, with a data retention of 40 years. The memory operates with a power sup- ply as low as 2.5 V. The M14C16 and M14C04 are each available in wafer form (either sawn or unsawn) and in micro- module form (on film). Each memory is compatible with the I2C memory standard. This is a two wire serial interface that Table 1. Signal Names SDA Serial Data/Address Input/ Output SCL Serial Clock WC Write Control VCC Supply Voltage GND Ground Micromodule (D20) Wafer Figure 1. Logic Diagram VCC SCL WC M14xxx GND SDA AI02217 March 1999 1/13 1 page M14C16, M14C04 Byte Write In the Byte Write mode, after the Device Select code and the address, the master sends one data byte. If the addressed location is write protected by the WC pin, the memory replies with a NoACK, and the location is not modified. If, instead, the WC pin has been held at 0, as shown in Figure 6, the memory replies with an ACK. The master termi- nates the transfer by generating a STOP condi- tion. Page Write The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory address bits (b10-b4 for the M14C16 and b8-b4 for the M14C04) are the same. The master sends from one up to 16 bytes of data, each of which is ac- knowledged by the memory if the WC pin is low. If the WC pin is high, each data byte is followed by a NoACK and the location is not modified. After each byte is transferred, the internal byte address coun- ter (the four least significant bits only) is incre- mented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could re- sult in data being overwritten. Note that, for any byte or page write mode, the generation by the master of the STOP condition starts the internal memory program cycle. This STOP condition trig- gers an internal memory program cycle only if the STOP condition is internally decoded immediately after the ACK bit; any STOP condition decoded out of this "10th bit" time slot will not trigger the in- ternal programming cycle. All inputs are disabled until the completion of this cycle and the Memory will not respond to any request. Minimizing System Delays by Polling On ACK During the internal write cycle, the memory discon- nects itself from the bus, and copies the data from its internal latches to the memory cells. The maxi- mum write time (tw) is indicated in Table 5, but the Figure 5. Write Mode Sequences with WC=1 WC BYTE WRITE ACK ACK NO ACK DEV SEL BYTE ADDR DATA IN R/W WC PAGE WRITE WC (cont'd) PAGE WRITE (cont'd) ACK ACK NO ACK NO ACK DEV SEL BYTE ADDR DATA IN 1 DATA IN 2 DATA IN 3 R/W NO ACK NO ACK DATA IN N AI02803B 5/13 5 Page Table 9. Ordering Information Scheme Example: M14C04 - W D20 M14C16, M14C04 Memory Capacity 16 16 Kbit 04 4 Kbit Operating Voltage W 2.5 V to 5.5 V Delivery Form D20 Module on Super 35 mm film W2 Unsawn wafer (275 µm ± 25 µm thickness) W4 Unsawn wafer (180 µm ± 15 µm thickness) S2x Sawn wafer (275 µm ± 25 µm thickness) S4x Sawn wafer (180 µm ± 15 µm thickness) where “x” indicates the sawing orientation, as follows (and as shown in Figure 11) 1 GND at top right 2 GND at bottom right 3 GND at bottom left 4 GND at top left ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all ‘1’s (FFh). The notation used for the device number is as shown in Table 9. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Sawn wafers are scribed and mounted in a frame on adhesive tape. The orientation is defined by the position of the GND pad on the die, viewed with active area of product visible, relative to the notch- es of the frame (as shown in Figure 11). The orien- tation of the die with respect to the plastic frame notches is specified by the Customer. One further concern, when specifying devices to be delivered in this form, is that wafers mounted on adhesive tape must be used within a limited pe- riod from the mounting date: – two months, if wafers are stored at 25°C, 55% relative humidity – six months, if wafers are stored at 4°C, 55% rel- ative humidity 11/13 11 Page

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