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PDF M12L64322A-6T Data sheet ( Hoja de datos )
| Número de pieza | M12L64322A-6T | |
| Descripción | 512K x 32 Bit x 4 Banks Synchronous DRAM | |
| Fabricantes | ETC | |
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ESMT
SDRAM
M12L64322A
512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6μs refresh interval
ORDERING INFORMATION
86 Pin TSOP (TypeII)
(400mil x 875mil)
Product No.
M12L64322A-6T
M12L64322A-7T
MAX FREQ.
166MHz
143MHz
PACKAGE
TSOPII
GENERAL DESCRIPTION
The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.
Synchronous design allows precise cycle control wi0th the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN ARRANGEMENT
Top View
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 VSS
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VDDQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VDDQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 N C
56 DQ31
55 VDDQ
54 DQ30
53 DQ29
52 VSSQ
51 DQ28
50 DQ27
49 VDDQ
48 DQ26
47 DQ25
46 VSSQ
45 DQ24
44 VSS
86Pin TSOP(II)
(400mil x 875mil)
(0.5mm Pin pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
1/44
1 page  
ESMT
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
M12L64322A
Unit
V
V
ns
V
Output
870 Ω
3.3V
1200 Ω
VOH (DC) =2.4V , IOH = -2 mA
30pF
VOL (DC) =0.4V , IOL = 2 mA
Output
Z0 =50 Ω
Vtt = 1.4V
50 Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time @ Operating
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
Version
-6 -7
12 14
18 18
18
42
100
60
1
2
1
20
42
63
Unit Note
ns 1
ns 1
ns 1
ns 1
us
ns 1
CLK 2
CLK 2
CLK 2
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
5/44
5 Page 
ESMT
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations.All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high) for
the duration of setup and hold time around positive edge of the
clock for proper functionality and Icc specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with
clock, the SDRAM enters the power down mode from the next
clock cycle. The SDRAM remains in the power down mode
ignoring the other inputs as long as CKE remains low. The
power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + tSS” before
the high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.
BANK ADDRESSES (BA0~BA1)
This SDRAM is organized as four independent banks of
524,288 words x 32 bits memory arrays. The BA0~BA1 inputs
are latched at the time of assertion of RAS and CAS to
select the bank to be used for the operation. The banks
addressed BA0~BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0~A10)
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0~A10).
The 11 row addresses are latched along with RAS and
BA0~BA1 during bank active command. The 8 bit column
addresses are latched along with CAS , WE and BA0~BA1
during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high , The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which require
more than single clock cycle like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
command decoder so that RAS , CAS , WE and all the
address inputs are ignored.
M12L64322A
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE =
“H”, DQM = “H” and the other pins are NOP condition at
the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for both banks of the
devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and WE (The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A10
and BA0~BA1 in the same cycle as CS , RAS , CAS
and WE going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all
banks are in the idle state. The mode register is divided
into various fields into depending on functionality. The
burst length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
vendor specific options or test mode use A7~A8,
A10/AP and BA0~BA1, A7~A9, A10/AP and BA0~BA1
must be set to low for normal SDRAM operation. Refer
to the table for specific codes for various burst length,
burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random
row in an idle bank. By asserting low on RAS and
CS with desired row and bank address, a row access
is initiated. The read or write operation can occur after a
time delay of tRCD (min) from the time of bank activation.
tRCD is the internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between
bank activate and read or write command should be
calculated by dividing tRCD (min) with cycle time of the
clock and then rounding of the result to the next higher
integer.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
11/44
11 Page | ||
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