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M1040-11I155.5200 fiches techniques PDF

Integrated Circuit Systems - VCSO BASED CLOCK PLL WITH AUTOSWITCH

Numéro de référence M1040-11I155.5200
Description VCSO BASED CLOCK PLL WITH AUTOSWITCH
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M1040-11I155.5200 fiche technique
Integrated
Circuit
Systems, Inc.
Preliminary Information
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Loss of Lock (LOL) indicator output
Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M1040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R Div
LOL
Phase
Detector
M / R Divider
LUT
PLL
Phase
Detector
M Divider
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL1
MR_SEL0
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44
77.76
155.52
622.08
8 155.52
2 or
1 77.76
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
VCSO
P Divider
(1 or 2)
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

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