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PDF 100353F Data sheet ( Hoja de datos )
| Número de pieza | 100353F | |
| Descripción | Low Power 8-Bit Register | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1998
100353
Low Power 8-Bit Register
General Description
The 100353 contains eight D-type edge triggered, master/
slave flip-flops with individual inputs (Dn), true outputs (Qn),
a clock input (CP), and a common clock enable pin (CEN).
Data enters the master when CP is LOW and transfers to the
slave when CP goes HIGH. When the CEN input goes HIGH
it overrides all other inputs, disables the clock, and the Q out-
puts maintain the last state.
The 100353 output drivers are designed to drive 50Ω termi-
nation to −2.0V. All inputs have 50 kΩ pull-down resistors.
Features
n Low power operation
n 2000V ESD protection
n Voltage compensated operating range = −4.2V to −5.7V
n Available to MIL-STD-883
Logic Symbol
Pin Names
D0– D7
CEN
CP
Q0– Q7
NC
Description
Data Inputs
Clock Enable Input
Clock Input (Active Rising Edge)
Data Outputs
No Connect
DS100316-4
© 1998 National Semiconductor Corporation DS100316
www.national.com
1 page  
Switching Waveforms
DS100316-8
FIGURE 2. Propagation Delay (Clock) and Transition Times
FIGURE 3. Setup and Pulse Width Times
DS100316-9
DS100316-10
Note 12: ts is the minimum time before the transition of the clock that information must be present at the data input.
Note 13: th is the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 4. Data Setup and Hold Time
5 www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 100353F.PDF ] | |
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