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PDF LXT972ALC Data sheet ( Hoja de datos )
| Número de pieza | LXT972ALC | |
| Descripción | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet | |
| Fabricantes | Intel Corporation | |
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LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Datasheet
The LXT972A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs).
This document also supports the LXT972.
The LXT972A supports full-duplex operation at 10Mbps and 100Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
s Combination 10BASE-T/100BASE-TX
Network Interface Cards (NICs)
Product Features
s 10/100 PCMCIA Cards
s Cable Modems and Set-Top Boxes
s 3.3V Operation.
s Low power consumption (300 mW
typical).
s 10BASE-T and 100BASE-TX using a
single RJ-45 connection.
s Supports auto-negotiation and parallel
detection.
s MII interface with extended register
capability.
s Robust baseline wander correction
performance.
s Standard CSMA/CD or full-duplex
operation.
s Configurable via MDIO serial port or
hardware control pins.
s Integrated, programmable LED drivers.
s 64-pin Low-profile Quad Flat Package
(LQFP).
— LXT972ALC - Commercial (0° to 70°C
ambient).
As of January 15, 2001, this document replaces the Level One document
LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet.
Order Number: 249186-002
January 2001
1 page  
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Figures
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LXT972A Block Diagram ....................................................................................... 9
LXT972A 64-Pin LQFP Assignments ..................................................................10
Management Interface Read Frame Structure ...................................................19
Management Interface Write Frame Structure ...................................................19
Interrupt Logic ....................................................................................................20
Initialization Sequence .......................................................................................22
Hardware Configuration Settings .......................................................................23
Link Establishment Overview .............................................................................25
10BASE-T Clocking ............................................................................................27
100BASE-X Clocking .........................................................................................27
Link Down Clock Transition ................................................................................27
Loopback Paths ..................................................................................................28
100BASE-X Frame Format ................................................................................29
100BASE-TX Data Path .....................................................................................29
100BASE-TX Reception with no Errors ..............................................................30
100BASE-TX Reception with Invalid Symbol .....................................................30
100BASE-TX Transmission with no Errors .......................................................31
100BASE-TX Transmission with Collision .........................................................31
Protocol Sublayers .............................................................................................32
LED Pulse Stretching .........................................................................................38
Typical Twisted-Pair Interface - Switch ...............................................................41
Typical Twisted-Pair Interface - NIC ...................................................................42
Typical MII Interface ...........................................................................................43
100BASE-TX Receive Timing - 4B Mode ...........................................................47
100BASE-TX Transmit Timing - 4B Mode ..........................................................48
10BASE-T Receive Timing .................................................................................49
10BASE-T Transmit Timing ................................................................................50
10BASE-T Jabber and Unjabber Timing ............................................................51
10BASE-T SQE (Heartbeat) Timing ...................................................................51
Auto Negotiation and Fast Link Pulse Timing ....................................................52
Fast Link Pulse Timing .......................................................................................52
MDIO Input Timing .............................................................................................53
MDIO Output Timing ..........................................................................................53
Power-Up Timing ................................................................................................54
RESET Pulse Width and Recovery Timing ........................................................54
PHY Identifier Bit Mapping .................................................................................60
LXT972A LQFP Package Specifications ............................................................70
Tables
1
2
3
4
5
6
7
8
LQFP Numeric Pin List.......................................................................................11
LXT972A MII Signal Descriptions........................................................................13
LXT972A Network Interface Signal Descriptions ................................................14
LXT972A Miscellaneous Signal Descriptions......................................................14
LXT972A Power Supply Signal Descriptions ......................................................15
LXT972A JTAG Test Signal Descriptions ...........................................................15
LXT972A LED Signal Descriptions......................................................................15
Hardware Configuration Settings ........................................................................24
Datasheet
5
5 Page 
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Table 1. LQFP Numeric Pin List
Pin Symbol
1 REFCLK/XI
2 XO
3 MDDIS
4 RESET
5 TxSLEW0
6 TxSLEW1
7 GND
8 VCCIO
9 N/C
10 N/C
11 GND
12 ADDR0
13 GND
14 GND
15 GND
16 GND
17 RBIAS
18 GND
19 TPOP
20 TPON
21 VCCA
22 VCCA
23 TPIP
24 TPIN
25 GND
26 GND
27 TDI
28 TDO
29 TMS
30 TCK
31 TRST
32 GND
33 PAUSE
34 TEST0
35 TEST1
36 LED/CFG3
Type
Reference for
Full Description
Input
Table 4 on page 14
Output Table 4 on page 14
Input
Table 2 on page 13
Input
Table 4 on page 14
Input
Table 4 on page 14
Input
Table 4 on page 14
– Table 5 on page 15
– Table 5 on page 15
– Table 4 on page 14
– Table 4 on page 14
– Table 5 on page 15
Input
Table 4 on page 14
– Table 5 on page 15
– Table 5 on page 15
– Table 5 on page 15
– Table 5 on page 15
Analog Input Table 4 on page 14
– Table 5 on page 15
Output Table 3 on page 14
Output Table 3 on page 14
– Table 5 on page 15
– Table 5 on page 15
Input
Table 3 on page 14
Input
Table 3 on page 14
– Table 5 on page 15
– Table 5 on page 15
Input
Table 6 on page 15
Output Table 6 on page 15
Input
Table 6 on page 15
Input
Table 6 on page 15
Input
Table 6 on page 15
– Table 5 on page 15
Input
Table 4 on page 14
Input
Table 4 on page 14
Input
Table 4 on page 14
I/O Table 7 on page 15
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT972ALC.PDF ] | |
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