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4015B Datasheet دیتاشیت PDF دانلود

دیتاشیت - Intersil Corporation - CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

شماره قطعه 4015B
شرح مفصل CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output
تولید کننده Intersil Corporation 
آرم Intersil Corporation 


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4015B شرح
CD4015BMS
December 1992
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Features
Pinout
• High-Voltage Type (20V Rating)
• Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V
• Fully Static Operation
• 8 Master-Slave Flip-Flops Plus Input and Output Buffering
• 100% Tested For Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range) =
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial-Input/Parallel-Output Data Queueing
• Serial to Parallel Data Conversion
• General-Purpose Register
Description
CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde-
pendent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, mas-
ter-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS’s is possible.
The CD4015BMS is supplied in these 16 lead outline pack-
ages:
CD4015BMS
TOP VIEW
CLOCK B 1
Q4B 2
Q3A 3
Q2A 4
Q1A 5
RESET A 6
DATA A 7
VSS 8
16 VDD
15 DATA B
14 RESET B
13 Q1B
12 Q2B
11 Q3B
10 Q4A
9 CLOCK A
Functional Diagram
DATA A
CLOCK A
RESET A
7
9
6
DATA B
CLOCK B
RESET B
15
1
14
VDD
16
4
STAGE
4
STAGE
5
Q1A
4
Q2A
3 Q3A
10 Q4A
13
Q1B
12
Q2B
11
Q3B
2
Q4B
8
VSS
Braze Seal DIP H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-89
File Number 3295

قانون اساسیصفحه 8
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