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Fairchild Semiconductor - Low Power Hex D-Type Flip-Flop

Numéro de référence 100351QI
Description Low Power Hex D-Type Flip-Flop
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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100351QI fiche technique
July 1988
Revised August 2000
100351
Low Power Hex D-Type Flip-Flop
General Description
The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and complement outputs, a pair of
common Clock inputs (CPa and CPb) and common Master
Reset (MR) input. Data enters a master when both CPa
and CPb are LOW and transfers to the slave when CPa and
CPb (or both) go HIGH. The MR input overrides all other
inputs and makes the Q outputs LOW. All inputs have
50 kpull-down resistors.
Features
s 40% power reduction of the 100151
s 2000V ESD protection
s Pin/function compatible with 100151
s Voltage compensated operating range:
4.2V to 5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100351SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100351PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100351QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100351QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (40°C to +85°C)
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
D0D5
CPa, CPb
MR
Q0Q5
Q0Q5
Description
Data Inputs
Common Clock Inputs
Asynchronous Master Reset Input
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS009885
28-Pin PLCC
www.fairchildsemi.com

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