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PDF 100341 Data sheet ( Hoja de datos )
| Número de pieza | 100341 | |
| Descripción | Low Power 8-Bit Shift Register | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1998
100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (Pn) and outputs (Qn) for parallel op-
eration, and with serial inputs (Dn) and steering logic for bidi-
rectional shifting. The flip-flops accept input data a setup
time before the positive-going transition of the clock pulse
and their outputs respond a propagation delay after this ris-
ing clock edge.
The circuit operating mode is determined by the Select in-
puts S0 and S1, which are internally decoded to select either
“parallel entry”, “hold”, “shift left” or “shift right” as described
in the Truth Table. All inputs have 50 kΩ pull-down resistors.
Features
n 35% power reduction of the 100141
n 2000V ESD protection
n Pin/function compatible with 100141
n Voltage compensated operating range = −4.2V to −5.7V
n Standard Microcircuit
Drawing (SMD) 5962-9459101
Logic Symbol
Pin Names
CP
S0, S1
D0, D7
P0– P7
Q0– Q7
Description
Clock Input
Select Inputs
Serial Inputs
Parallel Inputs
Data Outputs
DS100315-1
© 1998 National Semiconductor Corporation DS100315
www.national.com
1 page  
AC Electrical Characteristics (Continued)
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C
Min Max
ts
th
tpw(H)
Setup Time
Hold Time
Pulse Width HIGH
Dn, Pn
Sn
Dn, Pn
Sn
CP
0.60
1.70
0.90
0.50
2.00
TC = +25˚C
Min Max
0.60
1.60
0.90
0.50
2.00
TC = +125˚C Units
Min Max
Conditions
0.60
ns
2.40 Figure 4
0.90
ns
0.50
2.00 ns Figure 3
Notes
(Note 10)
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specifications which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C temperature (design characterization data).
Note 11: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
Test Circuitry
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1, L2 and L3 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
Pin numbers shown are for Flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
5
DS100315-6
www.national.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 100341.PDF ] | |
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