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PDF 100329PC Data sheet ( Hoja de datos )
| Número de pieza | 100329PC | |
| Descripción | Low Power Octal ECL/TTL Bidirectional Translator with Register | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1989
Revised August 2000
100329
Low Power Octal ECL/TTL Bidirectional Translator
with Register
General Description
The 100329 is an octal registered bidirectional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of the translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. The outputs change
synchronously with the rising edge of the clock input (CP)
even though only one output is enabled at the time.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces the termination power and prevents
loss of low state noise margin when several loads share
the bus.
The 100329 is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 kΩ pull-down resistors.
Features
s Bidirectional translation
s ECL high impedance outputs
s Registered outputs
s FAST TTL outputs
s 3-STATE outputs
s Voltage compensated operating range = −4.2V to −5.7V
s High drive IOS
Ordering Code:
Order Number Package Number
Package Description
100329PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100329QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100329QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP
28-Pin PLCC
FAST is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010583
www.fairchildsemi.com
1 page  
DIP ECL-to-TTL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF
Symbol
Parameter
TC = 0°C
Min Max
TC = 25°C
Min Max
fMAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSET
tHOLD
tPW(H)
Max Toggle Frequency
CP to Tn
OE to Tn
(Enable Time)
OE to Tn
(Disable Time)
DIR to Tn
(Disable Time)
En to CP
En to CP
Pulse Width CP
125 125
3.1 7.2 3.1 7.2
3.4 8.45 3.7 8.95
3.8 9.2 4.0 9.2
3.2 8.95 3.3 8.95
3.0 7.7 3.4 8.7
2.7 8.2 2.8 8.7
2.8 7.45 3.1 7.95
1.1 1.1
2.1 2.1
4.1 4.1
TC = 85°C
Min Max
125
3.3 7.7
4.0 9.7
4.3 9.95
3.5 9.2
4.1 9.95
3.1 8.95
4.0 9.2
1.1
2.6
4.1
Units
Conditions
MHz
ns
Figures 3, 4
ns Figures 3, 5
ns Figures 3, 5
ns Figures 3, 6
ns Figures 3, 4
ns Figures 3, 4
ns Figures 3, 4
PLCC and TTL-to-ECL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V
Symbol
Parameter
TC = 0°C
Min Max
TC = 25°C
Min Max
TC = 85°C
Min Max
Units
Conditions
fMAX
tPLH
tPHL
tPZH
Max Toggle Frequency
CP to En
OE to En
(Cutoff to HIGH)
350 350 350 MHz
1.7 3.4 1.7 3.5 1.9 3.7
ns Figures 1, 2
1.3 4.0 1.5 4.2 1.7 4.6
ns Figures 1, 2
tPHZ
OE to En
(HIGH to Cutoff)
1.5 4.3 1.6 4.3 1.6 4.4
ns Figures 1, 2
tPHZ
DIR to En
(HIGH to Cutoff)
1.6 4.1 1.6 4.1 1.7 4.3
ns Figures 1, 2
tSET
Tn to CP
1.0 1.0 1.0
ns Figures 1, 2
tHOLD
Tn to CP
1.7 1.7 1.9
ns Figures 1, 2
tPW(H)
Pulse Width CP
2.0 2.0 2.0
ns Figures 1, 2
tTLH Transition Time
0.6 1.6 0.6 1.6 0.6 1.6
ns Figures 1, 2
tTHL 20% to 80%, 80% to 20%
tOSHL
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
200 200 200 ps (Note 9)
Data to Output Path
tOSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
200 200 200 ps (Note 9)
Data to Output Path
tOST
Maximum Skew Opposite Edge
PLCC Only
Output-to-Output Variation
650 650 650 ps (Note 9)
Data to Output Path
tPS Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
650
650
650 ps (Note 9)
Data to Output Path
Note 9: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11 www.fairchildsemi.com
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