PDF DAC7625UB Data sheet ( Hoja de datos )

Número de pieza	DAC7625UB
Descripción	12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ® DAC7625 DAC7624 DAC7624 DAC7625 12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES q LOW POWER: 20mW q UNIPOLAR OR BIPOLAR OPERATION q SETTLING TIME: 10µs to 0.012% q 12-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C q RESET TO MID-SCALE (DAC7624) OR ZERO-SCALE (DAC7625) q DATA READBACK q DOUBLE-BUFFERED DATA INPUTS APPLICATIONS q PROCESS CONTROL q ATE PIN ELECTRONICS q CLOSED-LOOP SERVO-CONTROL q MOTOR CONTROL q DATA ACQUISITION SYSTEMS q DAC-PER-PIN PROGRAMMERS GND 12 I/O DB0-DB11 Buffer Input Register A DESCRIPTION The DAC7624 and DAC7625 are 12-bit quad voltage output digital-to-analog converters with guaranteed 12- bit monotonic performance over the specified tempera- ture range. They accept 12-bit parallel input data, have double-buffered DAC input logic (allowing simulta- neous update of all DACs), and provide a readback mode of the internal input registers. An asynchronous reset clears all registers to a mid-scale code of 800H (DAC7624) or to a zero-scale of 000H (DAC7625). The DAC7624 and DAC7625 can operate from a single +5V supply or from +5V and –5V supplies. Low power and small size per DAC make the DAC7624 and DAC7625 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7624 and DAC7625 are available in a 28-pin plastic double- wide or a 28-lead SOIC package, and offer guaranteed specifications over the –40°C to +85°C temperature range. VDD VREFH DAC Register A DAC A VOUTA Input Register B DAC Register B DAC B A0 A1 Control R/W Logic CS Input Register C DAC Register C DAC C Input Register D DAC Register D DAC D VOUTB VOUTC VOUTD RESET LDAC VREFL VSS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-11419C DAC762Pr4in/te7d 6in 2U.5S.A. April, 2000 ® 1 page TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) 0.50 0.25 0.00 –0.25 –0.50 0.50 0.25 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B) 0.50 0.25 0.00 –0.25 –0.50 0.50 0.25 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) 0.50 0.25 0.00 –0.25 –0.50 0.50 0.25 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.50 0.25 0.00 –0.25 –0.50 0.50 0.25 0.00 –0.25 –0.50 000H 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH 0.50 LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) 0.25 0.00 –0.25 +85°C –0.50 0.50 0.25 0.00 –0.25 –40°C –0.50 000H 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH 0.50 LINEARITY ERROR vs CODE (DAC B, –40°C and +85°C) 0.25 0.00 –0.25 +85°C –0.50 0.50 0.25 0.00 –0.25 –40°C –0.50 000H 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH ® 5 DAC7624/7625 5 Page DIGITAL TIMING Figure 3 and Table II provide detailed timing for the digital interface of the DAC7624 and DAC7625. DIGITAL INPUT CODING The DAC7624 and DAC7625 input data is in straight binary format. The output voltage is given by the following equa- tion: ( )VOUT = VREFL + VREFH – VREFL 4096 •N where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. CS tRDS R/W A0/A1 tAS Data Out tRCS tRDH tAH tDZ Data Valid tCSD Data Output Timing FIGURE 3. Digital Input and Output Timing. CS R/W A0/A1 LDAC Data In tDS RESET tWCS tWS tWH tAS tAH tLS tLH tLWD tDH tRESET Digital Input Timing SYMBOL DESCRIPTION tRCS tRDS tRDH tDZ tCSD tWCS tWS tWH tAS tAH tLS tLH tDS tDH tLWD tRESET CS LOW for Read R/W HIGH to CS LOW R/W HIGH after CS HIGH CS HIGH to Data Bus in High Impedance CS LOW to Data Bus Valid CS LOW for Write R/W LOW to CS LOW R/W LOW after CS HIGH Address Valid to CS LOW Address Valid after CS HIGH LDAC LOW to CS LOW LDAC LOW after CS HIGH Data Valid to CS LOW Data Valid after CS HIGH LDAC LOW RESET LOW TABLE II. Timing Specifications (TA = –40°C to +85°C). MIN TYP MAX 200 10 0 100 100 160 50 0 0 0 0 70 50 0 0 50 50 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® 11 DAC7624/7625 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
DAC7625U	12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER	Burr-Brown Corporation
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