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PDF DAC7612 Data sheet ( Hoja de datos )
| Número de pieza | DAC7612 | |
| Descripción | Dual/ 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DAC7612 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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®
DAC7612
DAC7612
Dual, 12-Bit Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q LOW POWER: 3.7mW
q FAST SETTLING: 7µs to 1 LSB
q 1mV LSB WITH 4.095V FULL-SCALE
RANGE
q COMPLETE WITH REFERENCE
q 12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
q 3-WIRE INTERFACE: Up to 20MHz Clock
q SMALL PACKAGE: 8-Lead SOIC
APPLICATIONS
q PROCESS CONTROL
q DATA ACQUISITION SYSTEMS
q CLOSED-LOOP SERVO-CONTROL
q PC PERIPHERALS
q PORTABLE INSTRUMENTATION
DESCRIPTION
The DAC7612 is a dual, 12-bit digital-to-analog con-
verter (DAC) with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It
requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and
high speed rail-to-rail output amplifiers. For a full-
scale step, each output will settle to 1 LSB within 7µs
while only consuming 3.7mW.
The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), Serial Data In (SDI), Chip Select (CS) and
Load DACs (LOADDACS) comprise the serial inter-
face.
The DAC7612 is available in an 8-lead SOIC package
and is fully specified over the industrial temperature
range of –40°C to +85°C.
VDD
LOADDACS
CS
CLK
SDI
12-Bit DAC A
12
DAC Register A
12
14-Bit Serial Shift Register
12
DAC Register B
12
12-Bit DAC B
Ref
VOUTA
VOUTB
DAC7612
GND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1501A
Printed in U.S.A. June, 1999
1 page  
TIMING DIAGRAMS
SDI
CLK
CS
LOADDACS
(MSB)
A1 A0 D11 D10 D9
D8 D7
D6 D5 D4
D3 D2
(LSB)
D1 D0
tCSS
tLD1
tCSH
tLD2
SDI
CLK
tDS
tCL
tDH
tCH
LOADDACS
FS
VOUT
ZS
tLDW
tS
±1 LSB
Error Band
LOGIC TRUTH TABLE
SERIAL SHIFT DAC
DAC
A1 A0 CLK CS LOADDACS REGISTER REGISTER A REGISTER B
XXXH
XX↑L
L X X H(1)
H L XH
HHXH
H No Change No Change
H Shifts One Bit No Change
L No Change Loads Serial
Data Word
L No Change Loads Serial
Data Word
L No Change No Change
↑ Positive Logic Transition; X = Don’t Care.
No Change
No Change
Loads Serial
Data Word
No Change
Loads Serial
Data Word
NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.
DATA INPUT TABLE
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TIMING SPECIFICATIONS
TA = –40°C to +85°C and VDD = +5V.
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tCH
Clock Width HIGH
30
tCL
Clock Width LOW
30
tLDW
Load Pulse Width
20
tDS
Data Setup
15
tDH
Data Hold
15
tLD1
Load Setup
15
tLD2
Load Hold
10
tCSS
Select
30
tCSH
Deselect
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
®
5 DAC7612
5 Page 
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion of
the DAC7612.
The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positive-
going signals.
The rail-to-rail output stage of the amplifier provides the full-
scale range of 0V to 4.095V while operating on a supply voltage
as low as 4.75V. In addition to its ability to drive resistive loads,
the amplifier will remain stable while driving capacitive loads
of up to 500pF. See Figure 3 for an equivalent circuit schematic
of the amplifier’s output driver and the Typical Performance
Curves section for more information regarding settling time,
load driving capability, and output noise.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7612 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (SDI, CLK, CS,
LOADDACS) as close as possible to either VDD or ground.
This will keep the CMOS inputs (see “Supply Current vs
Logic Input Voltages” in the Typical Performance Curves)
from shunting current between VDD and ground.
The DAC7612 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1µF capacitor taking
priority in this regard. The “Power Supply Rejection vs
Frequency” graph in the Typical Performance Curves sec-
tion shows the PSRR performance of the DAC7612. This
should be taken into account when using switching power
supplies or DC/DC converters.
In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7612 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
“VDD vs Load Current” graph in the Typical Performance
Curves section for more information.
Bandgap
Reference
2.435V
Buffer
R-2R DAC
2R
R
2R
R
2R
R
Output Amplifier
R2
R1
2R
2R
Typical of DAC A or DAC B
FIGURE 2. Simplified Schematic of Analog Portion.
P-Channel
N-Channel
VDD
VOUT
FIGURE 3. Simplified Driver Section of Output Amplifier.
11
GND
DAC7612
®
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DAC7612.PDF ] | |
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