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PDF 100314 Data sheet ( Hoja de datos )
| Número de pieza | 100314 | |
| Descripción | Low Power Quint Differential Line Receiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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February 1990
Revised August 2000
100314
Low Power Quint Differential Line Receiver
General Description
The 100314 is a monolithic quint differential line receiver
with emitter-follower outputs. An internal reference supply
(VBB) is available for single-ended reception. When used in
single-ended operation the apparent input threshold of the
true inputs is 25 mV to 30 mV higher (positive) than the
threshold of the complementary inputs. Unlike other F100K
ECL devices, the inputs do not have input pull-down resis-
tors.
Active current sources provide common-mode rejection of
1.0V in either the positive or negative direction. A defined
output state exists if both inverting and non-inverting inputs
are at the same potential between VEE and VCC. The
defined state is logic HIGH on the Oa–Oe outputs.
Features
s 35% power reduction of the 100114
s 2000V ESD protection
s Pin/function compatible with 100114
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Order Number Package Number
Package Description
100314SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100314PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100314QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100314QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
Da–De
Da–De
Oa–Oe
Oa–Oe
Description
Data Inputs
Inverting Data Inputs
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010260
28-Pin PLCC
www.fairchildsemi.com
1 page  
Test Circuit
Note:
• VCC, VCCA = +2V, VEE = −2.5V
• L1 and L2 = equal length 50Ω impedance lines
• RT = 50Ω terminator internal to scope
• Decoupling 0.1 µF from GND to VCC and VEE
• All unused outputs are loaded with 50Ω to GND
• CL = Fixture and stray capacitance ≤ 3 pF
Switching Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Propagation Delay and Transition Times
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 100314.PDF ] | |
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