DataSheetWiki


DDU4C-5060 fiches techniques PDF

ETC - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)

Numéro de référence DDU4C-5060
Description 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
Fabricant ETC 
Logo ETC 





1 Page

No Preview Available !





DDU4C-5060 fiche technique
5-TAP, HCMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU4C)
DDU4C
data
delay
3
®
devices, inc.
FEATURES
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
10 T2L fan-out capability
PACKAGES
IN 1 14 VCC
12 T1
T2 4
10 T3
T4 6
GND 7 8 T5
DIP
DDU4C-xx Comm.
DDU4C-xxM Military
IN
N/C
N/C
T2
N/C
T4
GND
1
2
3
4
5
6
7
14 VDD
13 N/C
12 T1
11 N/C
10 T3
9 N/C
8 T5
SMD
DDU4C-xxA2 Comm.
DDU4C-xxB2 Comm.
DDU4C-xxMC2 Military
FUNCTIONAL DESCRIPTION
The DDU4C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.
PIN DESCRIPTIONS
IN
T1-T5
VDD
GND
Signal Input
Tap Outputs
+5 Volts
Ground
SERIES SPECIFICATIONS
Minimum input pulse width: 20% of total delay
Output rise time: 8ns typical
Supply voltage: 5VDC ± 5%
Supply current: ICCL = 40µa typical
ICCH = 10ma typical
Operating temperature: 0° to 70° C
Temp. coefficient of total delay: 300 PPM/°C
DASH NUMBER SPECIFICATIONS
Part
Number
DDU4C-5050
DDU4C-5060
DDU4C-5075
DDU4C-5100
DDU4C-5125
DDU4C-5150
DDU4C-5200
DDU4C-5250
DDU4C-5300
DDU4C-5400
DDU4C-5500
Total
Delay (ns)
50 ± 2.5
60 ± 3.0
75 ± 4.0
100 ± 5.0
125 ± 6.5
150 ± 7.5
200 ± 10.0
250 ± 12.5
300 ± 15.0
400 ± 20.0
500 ± 25.0
Delay Per
Tap (ns)
10.0 ± 3.0
12.0 ± 3.0
15.0 ± 3.0
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
40.0 ± 4.0
50.0 ± 5.0
60.0 ± 6.0
80.0 ± 8.0
100.0 ± 10.0
NOTE: Any dash number between 5050 and 5500
not shown is also available.
20%
20%
20%
20%
20%
VDD IN
©1997 Data Delay Devices
T1 T2 T3 T4
DDU4C Functional diagram
T5 GND
Doc #97034
12/10/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1

PagesPages 4
Télécharger [ DDU4C-5060 ]


Fiche technique recommandé

No Description détaillée Fabricant
DDU4C-5060 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) ETC
ETC

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche