PDF LU6612-T64-DB Data sheet ( Hoja de datos )

Número de pieza	LU6612-T64-DB
Descripción	LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX
Fabricantes	Agere Systems
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Data Sheet July 2000 LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX Features General 10 Mbits/s Transceiver s Compatible with IEEE * 802.3u 10Base-T standard for twisted-pair cable s Autopolarity detection and correction s Adjustable squelch level for extended wire line length capability (2 levels) s Interfaces with IEEE 802.3u media independent interface (MII) s On-chip filtering eliminates the need for external fil- ters s Half- and full-duplex operations 100 Mbits/s Transceiver s Compatible with IEEE 802.3u MII (clause 22), PCS (clause 23), PMA (clause 24), autonegotiation (clause 28), and PMD (clause 25) specifications s Scrambler/descrambler bypass s Encoder/decoder bypass s 3-statable MII in 100 Mbits/s mode s Selectable carrier sense signal generation (CRS asserted during either transmission or reception in half duplex, CRS asserted during reception only in full duplex) s Selectable MII or 5-bit code group interface s Half- or full-duplex operations s On-chip filtering and adaptive equalization that eliminates the need for external filters s Autonegotiation (IEEE 802.3u clause 28): — Fast link pulse (FLP) burst generator — Arbitration function — Accepts preamble suppression — Operates up to 12.5 MHz s Supports the station management protocol and frame format (clause 22): — Basic and extended registers — Supports next-page function — Accepts preamble suppression — Operates up to 12.5 MHz s Supports the following management functions via pins if station management is unavailable: — Speed select — Encoder/decoder bypass — Scrambler/descrambler bypass — Full duplex — Autonegotiation s Supports half- and full-duplex operations s Provides four status signals: receive/transmit activ- ity, full duplex, link integrity, and speed indication s Powerdown mode for 10 Mbits/s and 100 Mbits/s operation s Loopback for 10 Mbits/s and 100 Mbits/s operation s 0.35 µm low-power CMOS technology s 64-pin TQFP s Single 5 V power supply * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product. 1 page Data Sheet July 2000 Description (continued) LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX 100 Mbits/s TRANSCEIVER TXD[3:0] 4B/5B ENCODER FAR-END FAULT GEN SCRAMBLER PDT PMD TX CRS COL RXD[3:0] RX_DV RX_ER/RXD[4] RX_CLK TX_CLK TXD[3:0] TX_EN TX_ER/TXD[4] MII REF10 RXC RXD TXC TEN TXD CLK20 MDC MDIO SD TX STATE MACHINE RX STATE SD COLLISION DETECT SD MACHINE CAR_STAT CIM CARRIER RXERR_ST DETECT 5B/4B DECODER ALIGNER FAR-END FAULT DETECT DESCRAMBLER 10 Mbits/s TRANSCEIVER LC10 LS10 LC100 LS100 MII MANAGEMENT AUTONEGOTIATION AND LINK MONITOR LSCLK DPLL 25 MHz 125 MHz 20 MHZ DCRU PDR SD Figure 2. Functional Block Diagram: Device Detail TX/TY PMD RX RX/RY 5-5136(F).cr1 Lucent Technologies Inc. 5 5 Page Data Sheet July 2000 LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX Pin Information (continued) Table 4. Ground and Power Pins (21) Signal VCCIOA GNDIOA VCCIOB GNDIOB GNDIOC VCCDIGA GNDDIGA VCCDIGB GNDDIGB VCCREC GNDREC VCCPLL GNDPLL VCCT GNDT VCCEQAP GNDEQAP VCCBG GNDBG VCCBT GNDBT Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Pin Description 6 Digital +5 V power supply for I/O 7 Digital ground for I/O 54 Digital +5 V power supply for I/O 53 Digital ground for I/O 41 Digital ground for I/O 35 Digital +5 V power supply for logic 36 Digital ground for logic 49 Digital +5 V power supply for logic 48 Digital ground for logic 60 Digital +5 V power supply for clock recovery circuit 59 Digital ground for clock recovery circuit 20 Analog +5 V power supply for 10 MHz and 100 MHz PLL clock synthesizer 23 Analog ground for 10 MHz and 100 MHz PLL clock synthesizer 11 Analog +5 V power supply for transmitter 10 Analog ground for transmitter 61 Analog +5 V power supply for equalizer and adaptation circuit 64 Analog ground for adaptation circuit. 1 Analog +5 V power supply for band-gap circuit 3 Analog ground band-gap circuit 14 Analog +5 V power supply for 10Base-T transmitter 13 Analog ground for 10Base-T transmitter Table 5. Miscellaneous Pins (20) Signal Type* Pin Description LSCLK1 LSCLK2 I O LINKLED/ I/O PHYAD[0] ACTLED/ I/O PHYAD[1] 21 Local Symbol Clock. 25 MHz clock, ±100 ppm, 40%—60% duty cycle. This input is connected to one terminal of a 25 MHz crystal or an external 25 MHz clock source. 22 Local Symbol Clock. 25 MHz crystal feedback. This output is connected to the other terminal of a 25 MHz crystal or an external 25 MHz. If LSCLK1 is driven from an external clock source, LSCLK2 is left unconnected. 4 Link LED. This pin indicates good link status. At powerup/reset, this pin is sampled as input and to set the PHYAD[0] bit. If pulled high through a resistor, this pin will set PHYAD[0] to a high or if pulled low through a resistor, will set PHYAD[0] to a zero. When this pin is pulled high the LED output will be active-low, when pulled low the LED output will be active-high. 5 Activity LED. This pin indicates transmit/receive activity. At powerup/reset, this pin is sampled as input to set the PHYAD[1] bit. If pulled high through a resistor, this pin will set PHYAD[1] to a high or if pulled low through a resistor, will set PHYAD[1] to a zero. When this pin is pulled high the LED output will be active-low, when pulled low the LED output will be active-high. * ↑ indicates there is an internal pull-up; ↓ indicates there is an internal pull-down. Lucent Technologies Inc. 11 11 Page

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