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PDF LU5X34F Data sheet ( Hoja de datos )
| Número de pieza | LU5X34F | |
| Descripción | Quad Gigabit Ethernet Transceiver | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Overview
The LU5X34F is a low-cost, low-power quad trans-
ceiver. It is used for data transmission over fiber or
coaxial media in conformance with IEEE * 802.3z
Gigabit Ethernet specification and Fibre Channel
ANSI † X3T11 at 1.0 Gbits/s and
1.25 Gbits/s.
Each of the four transceivers independently provides
complete serialize/deserialize (SERDES) and trans-
mit and receive functions. The device is available in a
217-pin PBGA package.
The transmitter section accepts TTL compatible data
at the 10-bit parallel input port. The parallel input
data is latched on the rising edge of TXCLKx. It also
accepts the low-speed, TTL compatible system
clock, REFCLK, and uses this clock to synthesize the
internal high-speed serial bit clock. The serialized
data is then available at the differential PECL out-
puts, terminated in 50 Ω or 75 Ω to drive either an
optical transmitter or coaxial media.
The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma-containing byte on the word
boundary, when ENCDET = 1.
s 100 MHz—125 MHz differential or single-ended
reference clock.
s 10-bit parallel, TTL-compatible I/O interface.
s 8-bit/10-bit encoded data.
s High-speed comma character recognition (K28.1,
K28.5, K28.7) for latency-sensitive applications
and alignment to word boundary.
s Two 50 MHz—62.5 MHz receive-byte clocks.
s Single analog PLL design requires no external
components for the frequency synthesizer.
s Novel digital data lock in receiver avoids the need
for multiple analog PLLs.
s Expandable beyond four serializer/deserializers.
s PECL high-speed interface I/O for use with optical
transceiver or coaxial copper media.
s Requires one external resistor for PECL output ref-
erence-level definition.
s Low-power digital CMOS technology.
s Less than 2 W total power dissipation per quad
transceiver.
s 3.3 V ± 5% power supply.
s 0 °C—70 °C ambient temperature.
s Stand-alone transceiver product.
s Transceiver macrocell template.
s Available in 217-pin PBGA package.
Features
s Designed to operate in Ethernet, fibre channel,
Firewire ‡, or backplane applications.
s Operationally compliant to IEEE 802.3z Gigabit
Ethernet specification.
s Operationally compliant to Fibre Channel ANSI
X3T11. Provides FC-0 services at 1.0 Gbits/s—
1.25 Gbits/s (10-bit encoded data rate).
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† ANSI is a registered trademark of American National Standards
Institute.
‡ FireWire is a registered trademark of Apple Computer, Inc.
1 page  
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Functional Description (continued)
Powerup Sequence
The power ramp time for the LU5X34F is specified at
VDD > 2.7 V within 20 µs of start-up. Once 2.7 V is
reached, the device is held in reset for 15 µs—70 µs.
The REFCLK must be active and within specification at
this point and remain active while the device is pow-
ered up, unless in Reset.
When signals RESET, BYPPLL, and LPWR are all low,
the following start-up sequence occurs:
1. 0 µs—32 µs, the analog PLL is held at minimum fre-
quency to allow dc bias to settle.
2. 32 µs—262 µs, the analog PLL has locked-in and
receiver analog circuits start to lock-in.
3. 262 µs—326 µs, the receiver analog circuits are
locked; receiver starts to lock onto incoming data.
4. After 358 µs, the receiver is locked onto incoming
data and can be viewed at the parallel output ports.
The comma-detect circuit is enabled at this point,
allowing byte alignment if ENCDET = 1.
If LCKREFN goes low after the 358 µs, the receiver will
sit idle. When LCKREFN goes high, the receiver will be
locked onto data after 2 µs.
Sleep Mode
The LU5X34F has a sleep mode that is activated by
enabling LPWR. In this mode, a divided-down version
of the REFCLK is used to refresh the dynamic circuits
within the transceiver. The PLL is powered down in this
mode also. LCKREFN can also be activated to reduce
the power even further. Note that complete powerdown
for IDDQ testing is not supported due to the dynamic
logic used in the high-speed sections of the trans-
ceiver. The lock-in sequence timing is needed when
coming out of sleep mode.
Device Reset
The RESETN input to the device is active-low. When
activated with a pulse duration of 1 µs, the RESETN sig-
nal globally resets the device and the following is per-
formed:
1. The single analog PLL is forced to operate at the mini-
mum frequency possible for its VCO. The PLL will not
be locked in this condition.
2. The HDOUTP, HDOUTN outputs are forced to a
PECL logic 0.
3. The deserializer clocks, but input data at HDINP,
HDINN is ignored and the RX[9:0] signals remain in
their previous state.
4. The phase interpolation/selection circuits are deacti-
vated and the selected phase is reset.
5. The receiver digital low-pass filter in the DPLL is reset.
Normally, a reset is not necessary for correct operation,
although a reset can aid rapid lock-in of the internal
PLL circuitry. This active-low pin is internally pulled
high.
Lucent Technologies Inc.
5
5 Page 
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Input/Output Information (continued)
Table 3c. Pinout—Channel C I/O
Name
TXC9
TXC8
TXC7
TXC6
TXC5
TXC4
TXC3
TXC2
TXC1
TXC0
RXC9
RXC8
RXC7
RXC6
RXC5
RXC4
RXC3
RXC2
RXC1
RXC0
TXCLKC
Pin I/O
T1 Input
R2
P3
N4
R1
P2
N3
M4
P1
N2
P6 Output
R5
U4
T5
R6
U5
T6
R7
P7
U6
U2 Input
RXCLK0C
RXCLK1C
ENCDETC
COMDETC
EWRAPC
LCKREFNC
HDINCP,
HDINCN
HDOUTCP,
HDOUTCN
LDSTC
P5
R4
L1
T4
K3
L4
L16, M17
M15, M16
L2
Output
Output
Input
Output
Input
Input
Input
Output
Input
Level
TTL/
CMOS
Description
Channel C, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked in on the rising edge of TXCLKC.
TXC0 is the LSB.
TTL/
CMOS
Channel C, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clocked-
out on the alternate rising edge of RXCLK0C,
RXCLK1C. RXC0 is the LSB.
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL
Transmit Clock (100 MHz—125 MHz).
Used to latch TXC[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel C, Byte-Align Clock 0.
Channel C, Byte-Align Clock 1.
Channel C, Enable-Comma Detect.
Channel C, Byte-Aligned Comma.
Channel C, Loopback at Serial I/O.
Channel C, Lock Receiver to Clock.
Channel C, Differential Serial Inputs.
PECL Channel C, Differential Serial Outputs.
TTL/ Channel C, Load Test[5:1] Inputs.
CMOS
Lucent Technologies Inc.
11
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