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PDF LTC695I-3.3 Data sheet ( Hoja de datos )
| Número de pieza | LTC695I-3.3 | |
| Descripción | 3.3V Microprocessor Supervisory Circuits | |
| Fabricantes | Linear Technology | |
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FEATURES
s UL Recognized ® File # E145770
s Guaranteed Reset Assertion at VCC = 1V
s Pin Compatible with LTC694/LTC695
for 3.3V Systems
s 200µA Typical Supply Current
s Fast (30ns Typ) On-Board Gating of
RAM Chip Enable Signals
s SO-8 and S16 Packages
s 2.90V Precision Voltage Monitor
s Power OK/Reset Time Delay: 200ms or Adjustable
s Minimum External Component Count
s 1µA Maximum Standby Current
s Voltage Monitor for Power-Fail or
Low-Battery Warning
s Thermal Limiting
s Performance Specified Over Temperature
U
APPLICATIO S
s 3.3V Low Power Systems
s Critical µP Power Monitoring
s Intelligent Instruments
s Battery-Powered Computers and Controllers
s Automotive Systems
LTC694-3.3/LTC695-3.3
3.3V Microprocessor
Supervisory Circuits
DESCRIPTIO
The LTC®694-3.3/LTC695-3.3 provide complete 3.3V
power supply monitoring and battery control functions.
These include power-on reset, battery back-up, RAM write
protection, power failure warning and watchdog timing.
The devices are pin compatible upgrades of the LTC694/
LTC695 that are optimized for 3.3V systems. Operating
power consumption has been reduced to 0.6mW (typical)
and 3µW maximum in battery back-up mode. Micropro-
cessor reset and memory write protection are provided
when the supply falls below 2.9V. The RESET output is
guaranteed to remain logic low with VCC as low as 1V.
The LTC694-3.3/LTC695-3.3 power the active RAMs with
a charge pumped NMOS power switch to achieve low
dropout and low supply current. When primary power is
lost, auxiliary power, connected to the battery input pin,
powers the RAMs in standby through an efficient PMOS
switch.
For an early warning of impending power failure, the
LTC694-3.3/LTC695-3.3 provide an internal comparator
with a user-defined threshold. An internal watchdog timer
is also available, which forces the reset pins to active
states when the watchdog input is not toggled prior to a
preset time-out period.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN ≥ 5V
+
51k
18k
LT1129-3.3
VIN VOUT
1µF OUT SENSE
3.3V
+
100µF
VCC VOUT
0.1µF LTC695-3.3
SHDN
GND
VBATT
2.4V
CE IN
CE OUT
RESET
PFO
PFI GND WDI
MICROPROCESSOR RESET, BATTERY BACK-UP,
RAM WRITE PROTECTION, POWER WARNING AND
WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR 3.3V MICROPROCESSOR SYSTEM
0.1µF
POWER TO µP
CMOS RAM POWER
µP
SYSTEM
DECODER OUTPUT
RAM CS
µP RESET
µP NMI
I/O LINE
100Ω
0.1µF
694/5-3.3 TA01
RESET Output Voltage vs
Supply Voltage
5
4
3
2
1
0
01 2 345
SUPPLY VOLTAGE (V)
694/5-3.3 TA02
1
1 page  
LTC694-3.3/LTC695-3.3
TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage vs Load Current
3.30
VCC = 3.3V
VBATT = 2.4V
3.25 TA = 25°C
3.20
SLOPE = 4.6Ω
3.15
3.10
3.05
3.00
0
10 20 30 40
LOAD CURRENT (mA)
50
694/5-3.3 G01
Output Voltage vs Load Current
2.40
VCC = 0V
VBATT = 2.4V
2.39 TA = 25°C
2.38
SLOPE = 90Ω
2.37
2.36
2.35
0
100 200 300 400
LOAD CURRENT (µA)
500
694/5-3.3 G02
Power-Fail Comparator
Response Time
3.5
3.0
VCC = 3.3V
TA = 25°C
2.5
2.0 VPFI +
1.5
1.3V –
PFO
30pF
1.0
0.5
0
1.305V
1.285V
VPFI = 20mV STEP
01 2 34 567 89
TIME (µs)
694/5-3.3 G04
Power-Fail Comparator
Response Time
3.5
3.0
VCC = 3.3V
TA = 25°C
2.5
2.0
1.5 VPFI +
1.0 1.3V –
0.5
0
PFO
30pF
1.315V
1.295V
VPFI = 20mV STEP
0 20 40 60 80 100 120 140 160 180
TIME (µs)
694/5-3.3 G05
Reset Active Time vs
Temperature
220
VCC = 3.3V
210
200
190
180
170
160
150
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
694/5-3.3 G07
Reset Voltage Threshold vs
Temperature
2.90
VCC = 3.3V
2.89
2.88
2.87
2.86
2.85
2.84
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
694/5-3.3 G08
Power Failure Input Threshold
vs Temperature
1.310
VCC = 3.3V
1.308
1.306
1.304
1.302
1.300
1.298
1.296
1.294
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
694/5-3.3 G03
Power-Fail Comparator
Response Time with Pull-Up
Resistor
3.5
3.0
VCC = 3.3V
TA = 25°C
2.5
2.0
3.3V
1.5
1.0
VPFI +
10k
PFO
0.5
1.3V –
30pF
0
1.315V
1.295V
VPFI = 20mV STEP
0 2 4 6 8 10 12 14 16 18
TIME (µs)
694/5-3.3 G06
RESET Output Voltage vs
Supply Voltage
5
4
3
2
1
0
01 2 345
SUPPLY VOLTAGE (V)
694/5-3.3 TA02
5
5 Page 
LTC694-3.3/LTC695-3.3
APPLICATI S I FOR ATIO
3.3V
0.1µF
2.4V
VCC VOUT +
LTC695-3.3
CE OUT
VBATT
GND
CE IN
RESET
RESET
10µF
0.1µF
VCC
62512
RAM
CSGND
30ns PROPAGATION DELAY
FROM DECODER
TO µP
694/5-3.3 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
3.3V
0.1µF
2.4V
VCC VOUT +
LTC694-3.3
10µF
VBATT RESET
GND
0.1µF
CS
VCC
62128
RAM
CS1
CS2
GND
694/5-3.3 F07
Figure 7. Write Protect for RAM with LTC694-3.3
VIN ≥ 5V
+
R1
51k
10µF
LT1129-3.3
VIN VOUT
OUT SENSE
SHDN
ADJ
R2
16k
3.3V
+
100µF 0.1µF
R3
200k
R4
10k
VCC
LTC694-3.3
LTC695-3.3
PFO
PFI GND
TO µP
694/5-3.3 F08
Figure 8. Monitoring Unregulated DC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
VIN ≥ 6.5V
+
10µF
LT1129-3.3
VIN VOUT
OUT SENSE
SHDN
ADJ
10µF
+
3.3V
R1 R4
27k 10k
R3
2.7M
R2
16k
R5
5k
0.1µF
VCC
LTC694-3.3
LTC695-3.3
PFO
PFI GND
TO µP
694/5-3.3 F09
Figure 9. Monitoring Regulated DC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
comparing the power failure input (PFI) with an internal
1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 3.3V output. The
voltage divider ratio can be chosen such that the voltage
at the PFI pin falls below 1.3V several milliseconds before
the 3.3V supply falls below the maximum reset voltage
threshold 3.0V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
VH
= 1 .3V
1+
R1
R2
+
RR31
When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.
VL
=
1.3V
1+
R1
R2
–
(3.3V – 1.3V)R1
1.3V(R3 + R4)
Assuming
R4 <<
R3,VHYSTERESIS
=
3.3
V
R1
R3
Example 1: The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input VIN is 100mV/ms and the total time to execute
a shutdown procedure is 8ms. Also the noise of VIN is
200mV. With these assumptions in mind, we can reason-
ably set VL = 5V which is 1.6V greater than the sum of
maximum reset voltage threshold and the dropout voltage
of the LT1129-3.3 (3V + 0.4V) and VHYSTERESIS = 850mV.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC695I-3.3.PDF ] | |
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