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PDF LTC695I Data sheet ( Hoja de datos )
| Número de pieza | LTC695I | |
| Descripción | Microprocessor Supervisory Circuits | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC695I (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
s UL Recognized ® File # E145770
s Guaranteed Reset Assertion at VCC = 1V
s 1.5mA Maximum Supply Current
s Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
s SO-8 and S16 Packaging
s 4.65V Precision Voltage Monitor
s Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
s Minimum External Component Count
s 1µA Maximum Standby Current
s Voltage Monitor for Power-Fail
or Low-Battery Warning
s Thermal Limiting
s Performance Specified Over Temperature
s Superior Upgrade for MAX690 Family
U
APPLICATIO S
s Critical µP Power Monitoring
s Intelligent Instruments
s Battery-Powered Computers and Controllers
s Automotive Systems
LTC690/LTC691
LTC694/LTC695
Microprocessor
Supervisory Circuits
DESCRIPTIO
The LTC®690 family provides complete power supply
monitoring and battery control functions for microproces-
sor reset, battery back-up, CMOS RAM write protection,
power failure warning and watchdog timing. A precise
internal voltage reference and comparator circuit monitor
the power supply line. When an out-of-tolerance condition
occurs, the reset outputs are forced to active states and the
chip enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
remain logic low even with VCC as low as 1V.
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop-
out and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
For an early warning of impending power failure, the
LTC690 family provides an internal comparator with a
user-defined threshold. An internal watchdog timer is also
available, which forces the reset pins to active states when
the watchdog input is not toggled prior to a preset time-out
period.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN ≥ 7.5V
+
10µF
LT ®1086-5
VIN VOUT
ADJ
5V
+
100µF
51k
10k
0.1µF
3V
VCC VOUT
LTC690/LTC691
LTC694/LTC695
VBATT
RESET
PFO
PFI GND WDI
0.1µF
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
0.1µF
POWER TO µP
CMOS RAM POWER
µP
SYSTEM
µP RESET
µP NMI
I/O LINE
100Ω
690 TA01
RESET Output Voltage vs
Supply Voltage
5
TA = 25°C
EXTERNAL PULL-UP = 10µA
4 VBATT = 0V
3
2
1
0
01 2 345
SUPPLY VOLTAGE (V)
690 TA02
1
1 page  
BLOCK DIAGRA
VBATT
VCC
CE IN
PFI
OSC IN
OSC SEL
WDI
M2
M1
–
C2
+
+
C1
–
1.3V
GND
–
C3
+
OSC
TRANSITION
DETECTOR
CHARGE
PUMP
RESET PULSE
GENERATOR
WATCHDOG
TIMER
LTC690/LTC691
LTC694/LTC695
VOUT
BATT ON
LOW LINE
CE OUT
PFO
RESET
RESET
WDO
690 BD
PI FU CTIO S
VCC: 5V Supply Input. The VCC pin should be bypassed
with a 0.1µF capacitor.
VOUT: Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1µF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
VBATT: Back-Up Battery Input. When VCC falls below VBATT,
auxiliary power, connected to VBATT, is delivered to VOUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, VBATT should be connected to GND.
GND: Ground pin.
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of VOUT. BATT ON goes
high when VOUT is internally switched to VBATT.
PFI: Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or VOUT when
C3 is not used.
5
5 Page 
LTC690/LTC691
LTC694/LTC695
APPLICATI S I FOR ATIO
5V
0.1µF
3V
VCC VOUT
LTC691
LTC695
CE OUT
VBATT CE IN
RESET
GND RESET
+
10µF
0.1µF
20ns PROPAGATION DELAY
FROM DECODER
TO µP
VCC
62512
RAM
CS
GND
690 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
0.1µF
3V
VCC VOUT
LTC690
LTC694
VBATT RESET
GND
+
10µF
0.1µF
CS
VCC
62128
RAM
CS1
CS2
GND
690 F07
Figure 7. Write Protect for RAM with LTC690 or LTC694
VIN ≥ 7.5V
+
10µF
R1
51k
R2
10k
LT1086-5
VIN VOUT
ADJ
+
100µF
R3
300k
5V
0.1µF
R4
10k
VCC
LTC690/LTC691
LTC694/LTC695
PFO
PFI GND
TO µP
690 F08
Figure 8. Monitoring Unregulated DC Supply
with the LTC690's Power-Fail Comparator
VIN ≥ 6.5V
+
10µF
LT1086-5
VIN VOUT
ADJ
+
10µF
5V
R1 R4
27k 10k
R3
2.7M
R2
8.2k
R5
3.3k
0.1µF
VCC
LTC690/LTC691
LTC694/LTC695
PFO
PFI GND
TO µP
1690 F09
Figure 9. Monitoring Regulated DC Supply
with the LTC690's Power-Fail Comparator
Power-Fail Warning
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor's
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microproces-
sor to execute shutdown procedure between PFO and
RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
VH
=
1.3V
1+
R1
R2
+
R1
R3
When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.
VL
=
1.3V
1 +
R1
R2
–
(5V – 1.3V)R1
1.3V(R3 + R4)
Assuming
R4
<<
R3, VHYSTERESIS
=
5V
R1
R3
Example 1: The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input VIN is 100mV/ms and the total time to execute
a shutdown procedure is 8ms. Also the noise of VIN is
200mV. With these assumptions in mind, we can reason-
ably set VL = 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC695I.PDF ] | |
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