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PDF HM6264B Data sheet ( Hoja de datos )
| Número de pieza | HM6264B | |
| Descripción | 64 k SRAM (8-kword x 8-bit) | |
| Fabricantes | Hitachi Semiconductor | |
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HM6264B Series
64 k SRAM (8-kword × 8-bit)
ADE-203-454B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HM6264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance
and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil
SOP (foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density
mounting.
Features
• High speed
Fast access time: 85/100 ns (max)
• Low power
Standby: 10 µW (typ)
Operation: 15 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Battery backup operation capability
1 page  
HM6264B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)
Parameter
Symbol Min Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
|ILO|
Operating power supply
current
Average operating power
supply current
I CCDC
I CC1
I CC2
Standby power supply
current
I SB
——2
µA Vin = VSS to VCC
——2
µA CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to VCC
—7
15 mA CS1 = VIL, CS2 = VIH, II/O = 0 mA
others = VIH/VIL
— 30 45 mA Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIH, II/O = 0 mA
others = VIH/VIL
— 3 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA
CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
— 1 3 mA CS1 = VIH, CS2 = VIL
I SB1
—2
50 µA CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
Output low voltage
VOL
— — 0.4 V
IOL = 2.1 mA
Output high voltage
VOH 2.4 — — V IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol Min Typ
Input capacitance*1
Cin — —
Input/output capacitance*1
CI/O — —
Note: 1. This parameter is sampled and not 100% tested.
Max
5
7
Unit
pF
pF
Test conditions
Vin = 0 V
VI/O = 0 V
5 Page 
HM6264B Series
Write Timing Waveform (2) (OE Low Fixed) (OE = VIL)
Address
CS1
tWC
Valid address
tAW
tCW
*1
tWR
CS2
WE
Dout
Din
tAS
High Impedance
tWP
tWHZ
tOW
tOH
*2
tDW tDH
*4
Valid data
*3
Notes:
1. If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs
remain in high impedance state.
2. Dout is the same phase of the written data in this write cycle.
3. Dout is the read data of the next address.
4. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input
signals of opposite phase to the outputs must not be applied to I/O pins.
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HM6264B.PDF ] | |
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