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PDF HM5225325F-B60 Data sheet ( Hoja de datos )
| Número de pieza | HM5225325F-B60 | |
| Descripción | 256M LVTTL interface SDRAM 100 MHz 1-Mword x 64-bit x 4-bank/2-Mword x 32-bit x 4-bank PC/100 SDRAM | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HM5225645F-B60
HM5225325F-B60
256M LVTTL interface SDRAM
100 MHz
1-Mword × 64-bit × 4-bank/2-Mword × 32-bit × 4-bank
PC/100 SDRAM
ADE-203-1014C (Z)
Rev. 1.0
Oct. 1, 1999
Description
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word × 64-bit × 4-bank. The Hitachi
HM5225325F is a 256-Mbit SDRAM organized as 2097152-word × 32-bit × 4-bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
• Single chip wide bit solution (× 64/× 32)
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Extremely small foot print: 1.27 mm pitch
Package: BGA (BP-108)
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 4/8/full page
• 2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
• Programmable CAS latency: 2/3
• Byte control by DQMB
1 page  
Pin Arrangement (HM5225325F)
HM5225645F-B60, HM5225325F-B60
108-bump BGA
12
A DQ31 NC
34 5 67
NC DQ24 VSS DQ23 NC
89
NC DQ16
B DQ30 NC NC DQ25 VCC DQ22 NC NC DQ17
C DQ29 NC
NC DQ26 VCC DQ21 NC
NC DQ18
D DQ28 NC
E
DQ
MB3
NC
NC DQ27 VSS DQ20 NC NC DQ19
DQ
MB2
NC
F CKE VCC
RAS WE
G A12 VCC
A10 A13
H A7 A5
VCC A1
J A4 VSS
A2 A3
K A8 A6
VSS A0
L A11 VSS
A9 CS
M Open CLK
VCC CAS
N
NC
DQ
MB0
NC
DQ
MB1
P DQ3 NC NC DQ4 VSS DQ11 NC NC DQ12
R DQ2 NC NC DQ5 VCC DQ10 NC NC DQ13
T DQ1 NC NC DQ6 VCC DQ9 NC NC DQ14
U DQ0 NC NC DQ7 VSS DQ8 NC NC DQ15
(Top view)
5
5 Page 
HM5225645F-B60, HM5225325F-B60
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are VIH or VIL fixed.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Min
Max Unit Notes
Input capacitance (CLK)
CI1
10
14
pF 1, 2, 4
Input capacitance
CI2 10 14 pF 1, 2, 4
(Input except DQM)
Input capacitance (DQM)
CI3
2.5
5
pF 1, 2, 4
Output capacitance (DQ)
CO
3
5
pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = VIH to disable Dout.
4. This parameter is sampled and not 100% tested.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HM5225325F-B60.PDF ] | |
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