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HM5212325F fiches techniques PDF

Hitachi Semiconductor - 128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM

Numéro de référence HM5212325F
Description 128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM
Fabricant Hitachi Semiconductor 
Logo Hitachi Semiconductor 





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HM5212325F fiche technique
HM5212325F-B60
128M LVTTL interface SDRAM
100 MHz
1-Mword × 32-bit × 4-bank
PC/100 SDRAM
ADE-203-1053A (Z)
Rev. 1.0
Oct. 18, 1999
Description
The Hitachi HM5212325F is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs
and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
Single chip wide bit solution (× 32)
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Extremely small foot print: 1.27 mm pitch
Package: BGA (BP-108)
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 4/8/full page
2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
Programmable CAS latency: 2/3
Byte control by DQMB
Refresh cycles: 4096 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh

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