PDF HPMX-5002-STR Data sheet ( Hoja de datos )

Número de pieza	HPMX-5002-STR
Descripción	IF Modulator/Demodulator IC
Fabricantes	Agilent(Hewlett-Packard)
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No Preview Available ! IF Modulator/Demodulator IC Technical Data HPMX-5002 Features • Use with HPMX-5001 Up/Down Converter Chip for DECT Telephone Applications • 2.7– 5.5 V Single Supply Voltage • >75 dB RSSI Range • Internal Data Slicer • On-chip LO Generation, Including VCO, Prescalers and Phase/ Frequency Detector • Flexible Chip Biasing, Including Standby Mode • Supports Reference Crystal Frequencies of 9, 12, and 16 Times the DECT Bit Rate (1.152 MHz) • IF Input Frequency Range up to 250 MHz • TQFP-48 Surface Mount Package Plastic TQFP-48 Package H9P4M6343X3–55002019 Pin Configuration 48 37 1 36 HPMX – 5002 9433 6435 12 13 019 25 24 Applications • DECT, Unlicensed PCS and ISM Band Handsets, Basestations and Wireless LANs 7-105 Description The Hewlett-Packard HPMX-5002 IF Modulator/Demodulator provides all of the active compo- nents necessary for the demodula- tion of a downconverted DECT signal. Designed specifically for DECT, the HPMX-5002 contains a down-conversion mixer (to a 2nd IF), limiting amplifier chain, discriminator/data slicer, lock detector, and RSSI circuits. The LO2 generation is also included on-chip, via a VCO, dividers, and phase/frequency detector. The divide ratios are programmable to support reference frequencies of either 9, 12, or 16 times the DECT bit rate of 1.152␣ MHz allowing the use of common, low cost crystals. The LO2 VCO can also be utilized in transmit mode by directly modulat- ing the external VCO tank. An AGC loop in the buffered VCO output suppresses harmonics and reduces signal level variability. The HPMX-5002 is designed to meet the size and power demands of portable applications. Battery cell count and cost are reduced due to the 2.7 V minimum supply voltage. The TQFP-48 package, combined with the high level of integration, means smaller footprints and fewer components. Flexible chip biasing takes full advantage of the power savings inherent in time-duplexed systems such as DECT. 5965-9106E 1 page HPMX-5002 Pin Description No. Mnemonic I/O Type 1 IFOP1 Analog O/P Description Output of IF amplifier, feeds quadrature network for discriminator 2 DMOD Analog I/P Input to discriminator mixer, driven by output of quadrature network 3 DMODOP Analog O/P Output of discriminator mixer, drives external low-pass data filter 4 BUF1 Analog I/P Noninverting input of buffer amplifier that drives the data slicer 5 BUF2 Analog O/P Output of buffer amplifer that drives the data slicer 6 TCNT Analog DC External capacitor connection which sets time constant for data slicer 7 TCSET CMOS I/P Data slicer time constant select 8 DATOP CMOS O/P Output bit stream from data slicer 9 RSSI Analog O/P Receive Signal Strength Indicator output 10 LKFIL Analog DC External capacitor connection which sets time constant for lock detector 11 LKDET CMOS O/P Indicates that LO2 PLL is in lock status 12 REF Analog I/P Reference signal for LO2 PLL 13 VCC3 DC Supply PLL supply voltage 14 VEE3 Ground PLL ground 15 DIV1 CMOS I/P Controls divide ratio for reference frequency input to the LO2 PLL 16 DIV2 CMOS I/P Controls divide ratio for reference frequency input to the LO2 PLL 17 DIV3 CMOS I/P Controls divide ratio for VCO frequency input to the LO2 PLL 20 PFD Analog O/P LO2 PLL phase/frequency detector charge pump output 21 VEE4 Ground LO2 VCO ground 22 VCC4 DC Supply LO2 VCO supply voltage 23 AGC Analog DC External capacitor connection to compensate LO2 VCO AGC loop 24 VCOA Analog I/P VCO tank force line 25 VCOB Analog O/P VCO tank sense line 26 VCOADJ Analog I/P Controls amplitude of buffered LO2 VCO output 27 OSCOP Analog O/P Buffered LO2 output (+) 28 OSCOPB Analog O/P Buffered LO2 output (-) 29 VCC5 DC Supply 1st IF supply voltage 30 VEE5 Ground 1st IF ground 31 IPDC Analog DC External capacitor connection for decoupling 1st IF bias point 32 IP1 Analog I/P 1st IF input signal 33 VCC1 DC Supply IF limiting amplifier supply voltage 34 VEE1 Ground IF limiting amplifier ground 35 IF1 Analog O/P Downconverted signal from front-end mixer, drives external filter (hi-Z output, open collector) 37 IFIP1 38 DC1A Analog I/P Analog DC Input to IF limiting amplifier, driven by external filter (600 Ω impedance, internally set) External capacitor connection for decoupling IF limiting amplifier 39 VCC2 DC Supply IF limiting amplifier supply voltage 40 VEE2 Ground IF limiting amplifier ground 7-109 5 Page Circuit in the IC Vcc DATAOP Small Signal Equivalent Circuit (typical values) Pin 8 Vcc RSSI Pin 9 Vcc 30 kΩ RSSI Vcc RSSI Pin 11 Vcc VCOB VCOA V Pins 24, 25 Vcc 65 Ω OSCOP OSCOP OSCOPS Pins 27, 28 OSCOPB V Figure 5. HPMX-5002 Internal and Equivalent Circuits, Pins 8, 9, 11, 24, 25, 27, and 28. 7-115 11 Page

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