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PDF HPC46100VF40 Data sheet ( Hoja de datos )
| Número de pieza | HPC46100VF40 | |
| Descripción | HPC46100 High-Performance microController with DSP Capability | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
June 1994
HPC46100 High-Performance microController
with DSP Capability
General Description
The HPC46100 is a member of the HPCTM family of High
Performance microControllers Each member of the family
has a similar core CPU with unique memory resources and
I O configuration to suit specific applications The
HPC46100 is fabricated in National’s advanced microCMOS
technology This process combined with an advanced archi-
tecture provides fast flexible I O control efficient data ma-
nipulation high speed computation and low power con-
sumption
Throughput is enhanced by operating the HPC46100 at fre-
quencies up to 40 MHz by integrating a Multiply Accumu-
late Unit (MAU) onto the chip and by optimizing instructions
to increase efficiency These features increase performance
in closed loop digital servo and filter applications
The HPC devices are complete microcomputers on a single
chip All system timing internal logic RAM and I O are
provided on the chip to produce a cost effective solution
for high performance applications On-chip functions
such as an MAU unit PWM outputs Chip Select Signals
UART up to seven 16-bit timers with input capture
capability WATCHDOGTM logic vectored interrupts and
MICROWIRE PLUSTM provide a high level of system inte-
gration The ability to directly address up to 64 kbytes of
memory enables the HPC to be used in powerful applica-
tions typically performed by microprocessors and peripheral
chips
(Continued)
Features
Y Multiply Accumulate Unit for fast signed multiply or mul-
tiply-accumulate
Y High speed 16 bit timers with PWM outputs or input
capture logic
Y 4 Chip select output logic with programmable control
Y 8-channel 8-bit A D Converter
Y 1024 bytes of on-chip 0 wait state RAM
Y FAST 100 ns for fastest instruction when using
40 0 MHz clock
Y Very low power with two power save modes IDLE and
HALT
Y UART full duplex with a programmable baud rate gen-
erator and parity checking detection
Y MICROWIRE PLUS serial I O interface
Y 8 vectored interrupt sources
Y Signed overflow flag for add and subtract instructions
Y 16 x 16 multiply and 32 x 16 divide
Y 16-bit architecture with byte and word operations
Y 64 kbytes of direct memory addressing
Y 8- or 16-bit wide external memory
Y Program instructions can be executed from RAM
Y Up to 31 general purpose I O lines that are memory
mapped
Y WATCHDOG logic
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
HPCTM WATCHDOGTM MICROWIRE PLUSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL DD11289
TL DD 11289 – 1
RRD-B30M105 Printed in U S A
1 page  
40 MHz (Continued)
AC Electrical Characteristics (Continued)
See Notes 1 and 4 and Figure 1 thru Figure 5 VCC e 5 0V g10% unless otherwise specified TA e 25 C one wait state
Symbol
Parameter
Min Max Units
E SIGNAL TIMING PARAMETERS
tRWSE e 0 25 tC b 7
tRWHE e 0 5 tC b 7
tASE e tC b 20
tRDE e WS b 20
WR Falling Edge to E Rising Edge
E Falling Edge to WR Rising Edge
Address Valid to E Rising Edge
E Falling Edge to Data Input Valid
SLOW PERIPHERAL TIMING PARAMETERS
55
18
30
30
ns
ns
ns
ns
tPLL e tC b 5
tPST e 0 75 tC b 10
tPVL e 0 75 tC b 15
tPVP e 0 75 tC b 10
tPCSA e 0 25 tC b 12 5
tPAS e 1 5 tC b 20
tPCSS e tC b 15
tPCSH e 0 5 tC b 15
tPACC e 5 tC b 25
tPRD e 3 5 tC b 25
tPDR e tC (max)
tPRW e 3 5 tC b 15
tPSW e 3 0 tC b 20
tPHW e tC b 20
tPWW e 3 5 tC b 15
PALE Pulse Width
Address Valid to PALE Falling Edge
Address Hold from PALE Falling Edge
PALE Falling Edge to RD or WR Falling Edge
Chip Select Setup to PALE Falling Edge
Address Setup to RD or WR Falling Edge
Chip Select Setup to RD or WR Falling Edge
Chip Select Hold from RD or WR Rising Edge
Address Valid to Input Data Valid
RD Falling Edge to Data In Valid
Data Hold after RD Rising Edge
RD Strobe Width
Data Setup before WR Rising Edge
Data Hold after WR Rising Edge
WR Strobe Width
45
27 5
22 5
27 5
0
55
35
10
0
160
130
30
160
225
150
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note CL e 40 pF
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (tCKIR and tCKIL) on CKI input less than 2 5 ns
Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle begin executed If HLD falling
edge occurs later tHAE as long as (3 tC a 4 WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input
Note 4 WS (tWAIT) x (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC e 40 MHz with
one wait state programmed
Note 5 Due to testing limitations actual limits will be better
5
5 Page 
Timing Waveforms (Continued)
TL DD 11289 – 12
FIGURE 11 Slow Peripheral Bus Timing
11
TL DD 11289 – 13
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HPC46100VF40.PDF ] | |
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