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PDF HMU16 Data sheet ( Hoja de datos )
| Número de pieza | HMU16 | |
| Descripción | 16 x 16-Bit CMOS Parallel Multiplier | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HMU16 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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HMU16/883
April 1997
16 x 16-Bit CMOS Parallel Multiplier
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product
• High-Speed (45ns) Clocked Multiply Time
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1MHz
• HMU16/883 is Compatible with the AM29516, LMU16,
IDT7216, and the CY7C516
• Supports Two’s Complement, Unsigned Magnitude
and Mixed Mode Multiplication
• TTL Compatible Inputs/Outputs
• Three-State Outputs
Ordering Information
PART NUMBER
HMU16GM-45/883
HMU16GM-60/883
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
PACKAGE
68 Ld CPGA
68 Ld CPGA
PKG.
NO.
N68.95
N68.95
Description
The HMU16/883 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier ideal for fast, real time digital signal pro-
cessing applications. The 16-bit X and Y operands may be
independently specified as either two’s complement or
unsigned magnitude format, thereby, allowing mixed mode
multiplication operations.
Additional inputs are provided to accommodate format
adjustment and rounding of the 32-bit product. The Format
Adjust control allows the user to select a 31-bit product with
the sign bit replicated in the LSP. The round control provides
for rounding the most significant portion of the result by add-
ing one to the most significant bit of the LSP.
Two 16-bit Output Registers (MSP and LSP) are provided to
hold the most and least significant portions of the result,
respectively. These registers may be made transparent for
asynchronous operation through the use of the Feedthrough
Control (FT). The two halves of the product may be routed to
a single 16-bit three-state output port via the output multi-
plexer control, and in addition, the LSP is connected to the Y-
input port through a separate three-state buffer.
The HMU16/883 utilizes independent clock signals (CLKX,
CLKY, CLKL, CLKM) to latch the input operands and output
Product Registers. This configuration maximizes throughput
and simplifies bus interfacing. All outputs of the HMU16/883
also offer three-state control for multiplexing onto multi-use
system busses.
Functional Diagram
X0-15 TCX
RND
TCY Y0-15/P0-15
REGISTER
CLKX
CLKY
FA
FT
CLKM
CLKL
MSPSEL
OEP
REGISTER
REGISTER
OEL
MULTIPLIER ARRAY
FORMAT ADJUST
MSP
LSP
REGISTER REGISTER
MULTIPLEXER
P16-31/P0-15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-29
File Number 2804.2
1 page  
HMU16/883
Burn-In Circuit
68 LEAD CPGA
TOP VIEW
11 N/C X13 X15 RND TCY VCC GND FT OEP
10 X11
X12
X14 CLKX TCX
VCC
GND
MSP
SEL
FA CLKM N/C
9 X9 X10
P30/ P31/
P14 P15
8 X7
X8
P28/ P29/
P12 P13
7 X5
X6
P26/ P27/
P10 P11
6 X3
X4
P24/P8 P25/P9
5 X1
X2
P22/P6 P23/P7
4 OEL X0
P20/P4 P21/P5
3 CLKY CLKL
P18/P2 P19/P3
2
N/C
Y0/P0 Y2/P2 Y4/P4 Y6/P6 Y8/P8
Y10/
P10
Y12/
P12
Y14/
P14
P16/P0 P17/P1
1
Y1/P1 Y3/P3 Y5/P5 Y7/P7 Y9/P9
Y11/
P11
Y13/
P13
Y15/
P15
N/C
A B CD E F GH J K L
CPGA PIN
B6
A6
B5
A5
B4
A4
B3
A3
B2
B1
C2
C1
D2
D1
E2
E1
F2
F1
G2
PIN NAME
X4
X3
X2
X1
X0
OEL
CLKL
CLKY
Y0/P0
Y1/P1
Y2/P2
Y3/P3
Y4/P4
Y5/P5
Y6/P6
Y7/P7
Y8/P8
Y9/P9
Y10/P10
BURN-IN SIGNAL
F6
F5
F4
F3
F2
VCC
F0
F0
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
CPGA PIN
G1
H2
H1
J2
J1
K2
L2
K3
L3
K4
L4
K5
L5
K6
L6
K7
L7
K8
L8
PIN NAME
Y11/P11
Y12/P12
Y13/P13
Y14/P14
Y15/P15
P0/P16
P1/P17
P2/P18
P3/P19
P4/P20
P5/P21
P6/P22
P7/P23
P8/P24
P9/P25
P10/P26
P11/P27
P12/P28
P13/P29
BURN-IN SIGNAL
F13
F14
F15
F4
F5
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
3-33
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HMU16.PDF ] | |
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