|
|
PDF HMP8156 Data sheet ( Hoja de datos )
| Número de pieza | HMP8156 | |
| Descripción | NTSC/PAL Encoder | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HMP8156 (archivo pdf) en la parte inferior de esta página. Total 33 Páginas | ||
|
No Preview Available !
HMP8156
August 1997
NTSC/PAL Encoder
Features
• (M) NTSC and (B, D, G, H, I, M, N, CN) PAL Operation
• ITU-R BT.601 and Square Pixel Operation
• Digital Input Formats
- 4:2:2 YCbCr
- 8-Bit or 16-Bit
- 4:4:4 RGB
- 16-Bit (5, 6, 5) or 24-Bit (8, 8, 8)
- Linear or Gamma-Corrected
- 8-Bit Parallel ITU-R BT.656
- Seven Overlay Colors
• Analog Output Formats
- Y/C + Two Composite
- RGB + Composite (SCART)
• Flexible Video Timing Control
- Timing Master or Slave
- Selectable Polarity on Each Control Signal
- Programmable Blank Output Timing
- Field Output
• Closed Caption Encoding for NTSC and PAL
• 2x Upscaling of SIF Video
• Four 2x Oversampling, 10-Bit DACs
• I2C Interface
• Verilog Models Available . . . . . . . . . . . . . . . . . . . . . . . . .
Applications
• Multimedia PCs
• Video Conferencing
• Video Editing
• Related Products
- NTSC/PAL Encoders: HMP8154
- NTSC/PAL Decoders: HMP8112A, HMP8115
Ordering Information
Description
The HMP8156 NTSC and PAL encoder is designed for use
in systems requiring the generation of high-quality NTSC
and PAL video from digital image data.
YCbCr or RGB digital video data drive the P0-P23 inputs.
Overlay inputs are processed and the data is 2x upsampled.
The Y data is optionally lowpass filtered to 5MHz and drives
the Y analog output. Cb and Cr are each lowpass filtered to
1.3MHz, quadrature modulated, and summed. The result
drives the C analog output. The digital Y and C data are also
added together and drive the two composite analog outputs.
The YCbCr data may also be converted to RGB data to drive
the DACs, allowing support for the European SCART con-
nector.
The DACs can drive doubly-terminated (37.5Ω) lines, and
run at a 2x oversampling rate to simplify the analog output
filter requirements.
Table of Contents
Page
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pixel Data Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . 3
Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pixel Input and Control Signal Timing. . . . . . . . . . . . . . . . 5
Video Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Host Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Evaluation Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TEMP.
PART NUMBER RANGE (oC) PACKAGE
PKG. NO.
HMP8156CN
0 to 70 64 PQFP
Q64.14x14
HMP8156EVAL1 Daughter Card Evaluation Platform (Note)
HMP8156EVAL2 Frame Grabber Evaluation Platform (Note)
NOTE: Described in the Applications Section
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 4269.3
1 page  
HMP8156
TABLE 3. OVERLAY MIXING FACTORS
M1, M0
% OVERLAY
COLOR
% PIXEL
COLOR
00 0 100
01 12.5 87.5
10 87.5 12.5
11 100
0
In external mixing mode, there is no minimum number of pix-
els an overlay color or pixel color must be selected. The mix-
ing level may also vary at any rate.
Overlay Mixing: Internal
Mixing of overlay and pixel data may also be controlled inter-
nally, and the M1 and M0 input pins are ignored. A transition
from pixel data to overlays, from overlays to pixel data, or
between different overlay colors triggers the mixing function.
An overlay color must be selected for a minimum of three
pixels for proper overlay operation in this mode. Internal
overlay mixing should not be used with the BT.656 input for-
mat.
When going from pixel to overlay data, mixing starts one pixel
before the selection of the overlay color (OL2-OL1!= 000). The
first pixel output before the overlay uses 12.5% overlay color
plus 87.5% pixel color. The next output is aligned with the
selection of the overlay color and uses 87.5% overlay color
plus 12.5% pixel color. Additional outputs use 100% overlay
color.
When going from overlay to pixel data, mixing starts one
pixel before the selection of the pixel color (OL2-OL0 = 000).
The last pixel output of the overlay uses 87.5% overlay color
plus 12.5% pixel color. The next output uses 12.5% overlay
color plus 87.5% pixel color. Additional outputs use 100%
pixel color.
When going from one overlay color to another, mixing starts
one pixel before the selection of the new overlay color, and
uses 12.5% new overlay color plus 87.5% old overlay color.
The next output is aligned with the selection of the new over-
lay color and uses 87.5% new overlay color plus 12.5% old
overlay color. Additional outputs use 100% new overlay
color.
Overlay Mixing: No Mixing
With no overlay mixing selected, whenever the OL0-OL2
inputs are non-zero, the overlay color is displayed. The M0
and M1 inputs are ignored, and no internal mixing is done.
Essentially, this is a hard switch between overlay and pixel
data. In this mode, there is no minimum number of pixels an
overlay color or pixel color must be selected.
This mode of operation allows SIF video to be upscaled to
full resolution and recorded on a VCR or displayed on a TV.
The input pixel data rate is reduced by half when 2X upscal-
ing is enabled. The color space conversion generates, and
the overlay mixer uses, 2:2:2 YCbCr data instead of 4:4:4
data. For rectangular pixel NTSC and PAL video, the input
rate is 6.75MHz during the active portion of each line instead
of 13.5MHz. Example SIF input resolutions and resulting
output resolutions are shown in Table 4.
TABLE 4. TYPICAL RESOLUTIONS FOR 2X UPSCALING
INPUT ACTIVE
RESOLUTION
352 x 240
352 x 288
320 x 240
384 x 288
OUTPUT ACTIVE
RESOLUTION
704 x 480
704 x 576
640 x 480
768 x 576
The HMP8156 performs horizontal 2X upscaling by linear
interpolation. The vertical scaling is done by line duplication.
For typical line duplication, the same frame of SIF pixel input
data is used for both the odd and even fields. Note that a
frame of SIF size input has about the same number of lines
as a field of full size input. After 2X upscaling, the input is
4:4:4 YCbCr data ready for video processing.
Pixel Input and Control Signal Timing
The pixel input timing and the video control signal input/out-
put timing of the HMP8156 depend on the part’s operating
mode. The periods when the encoder samples its inputs and
generates its outputs are summarized in Table 5.
Figures 1-9 show the timing of CLK, CLK2, BLANK, and the
pixel and overlay input data with respect to each other.
BLANK may be an input or an output; the figures show both.
When it is an input, BLANK must arrive coincident with the
pixel and overlay input data; all are sampled at the same
time.
When BLANK is an output, its timing with respect to the pixel
and overlay inputs depends on the blank timing select bit in
the timing_I/O_1 register. If the bit is cleared, the HMP8156
deasserts BLANK one CLK cycle before it samples the pixel
and overlay inputs. As shown in the timing figures, the
encoder samples the inputs 1-7 CLK2 periods after negating
BLANK, depending on the operating mode.
If the bit is set, the encoder deasserts BLANK during the
same CLK cycle in which it samples the input data. In effect,
the input data must arrive one CLK cycle earlier than when
the bit is cleared. This mode is not shown in the figures.
2X Upscaling
Following overlay processing, 2X upscaling may optionally
be applied to the pixel data. In this mode, the HMP8156
accepts SIF resolution video at 50 or 59.94 frames per sec-
ond and generates standard interlaced video at 262.5 lines
per field (240 active) at 59.94 fields per second for (M,
NSM) NTSC and (M) PAL, and 312.5 lines per field (288
active) at 50 fields per second for (B, D, G, H, I, N, CN) PAL.
5
5 Page 
HMP8156
BLANK Timing
The encoder uses the HSYNC, VSYNC, FIELD signals to
generate a standard composite video waveform with no
active video. The signal includes only sync tips, color burst,
and optionally, a 7.5 IRE blanking setup. Based on the
BLANK signal, the encoder adds the pixel and overlay input
data to the video waveform.
The encoder ignores the pixel and overlay input data when
BLANK is asserted. Instead of the input data, the encoder
generates the blanking level. The encoder also ignores the
pixel and overlay inputs when generating closed captioning
data on a specific line, even if BLANK is negated.
There must be an even number of active and total pixels per
line. In the 8-bit YCbCr modes, the number of active and
total pixels per line must be a multiple of four. Note that if
BLANK is an output, half-line blanking on the output video
cannot be done.
The HMP8156 never adds a 7.5 IRE blanking setup during
the active line time on scan lines 1-21 and 263-284 for (M,
NSM) NTSC, scan lines 523-18 and 260-281 for (M) PAL,
and scan lines 623-22 and 311-335 for (N) PAL, allowing the
generation of video test signals, timecode, and other infor-
mation by controlling the pixel inputs appropriately.
The relative timing of BLANK, HSYNC, and the output video
depends on the blanking and sync I/O directions. The typical
timing relation is shown in Figure 12. The delays which vary
with operating mode are indicated. The width of the compos-
ite sync tip and the location and duration of the color burst
are fixed based on the video format.
COMPOSITE
VIDEO OUT
HSYNC
The zero count for horizontal blanking is 32 CLK2 cycles
before the 50% point of the composite sync. From this zero
point, the HMP8156 counts every other CLK2 cycle. When
the count reaches the value in the start_h_blank register, the
encoder negates BLANK. When the count reaches the value
in the end_h_blank register, BLANK is asserted. There may
be an additional 0-7 CLK2 delays in modes which use CLK.
The data pipeline delay through the HMP8156 is 26 CLK2
cycles. In operating modes which use CLK to gate the inputs
into the encoder, the delay may be an additional 0-7 CLK2
cycles. The delay from BLANK to the start or end of active
video is an additional one-half CLK cycle when the blank tim-
ing select bit is cleared. The active video may also appear to
end early or start late since the HMP8156 controls the blank-
ing edge rates.
The delay from the active edge of HSYNC to the 50% point
of the composite sync is 4-39 CLK2 cycles depending on the
HMP8156 operating mode. The delay is shortest when the
encoder is the timing master; it is longest when in slave
mode.
CLK2 Input
The CLK2 input clocks all of the HMP8156, including its
video timing counters. For proper operation, all of the
HMP8156 inputs must be synchronous with CLK2. The fre-
quency of CLK2 depends on the device’s operating mode
and the total number of pixels per line. The standard clock
frequencies are shown in Table 7.
Note that the color subcarrier is derived from the CLK2 input.
Any jitter on CLK2 will be transferred to the color subcarrier,
resulting in color changes. Just 400ps of jitter on CLK2
causes up to a 1o color subcarrier phase shift. Thus, CLK2
should be derived from a stable clock source, such as a
crystal. The use of a PLL to generate CLK2 is not recom-
mended.
BLANK
DATA PIPE
DELAY
START H BLANK
SYNC DELAY
FIGURE 12. HSYNC, BLANK, AND OUTPUT VIDEO TIMING
When BLANK is an output, the encoder asserts it during the
inactive portions of active scan lines and for all of each inac-
tive scan line. The inactive scan lines blanked each field are
determined by the start_v_blank and end_v_blank registers.
The inactive portion of active scan lines is determined by the
start_h_blank and end_h_blank registers.
11
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet HMP8156.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HMP8154 | NTSC/PAL Encoders | Intersil Corporation |
| HMP8154CN | NTSC/PAL Encoders | Intersil Corporation |
| HMP8154EVAL1 | NTSC/PAL Encoders | Intersil Corporation |
| HMP8156 | NTSC/PAL Encoder | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |