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PDF HV9120 Data sheet ( Hoja de datos )
| Número de pieza | HV9120 | |
| Descripción | Current-Mode PWM Controller | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
HV9120
High-Voltage,
Current-Mode PWM Controller
Features
► 10 to 450V input voltage range
► <1.3mA supply current
► >1.0MHz clock
► >20:1 dynamic range @ 500KHz
► 49% Maximum duty cycle version
► Low internal noise
Applications
► Off-line high frequency power supplies
► Universal input power supplies
► High density power supplies
► Very high efficiency power supplies
► Extra wide load range power supplies
General Description
The Supertex HV9120 is a Switch Mode Power Supply
(SMPS) controller subsystem that can start and run directly
from almost any DC input, from a 12V battery to a rectified
and filtered 240V AC line. It contains all the elements
required to build a single-switch converter except for the
switch, magnetic assembly, output rectifier(s) and filter(s).
A unique input circuit allows the HV9120 to self-start
directly from a high voltage input, and subsequently
take the power to operate from one of the outputs of the
converter it is controlling, allowing very efficient operation
while maintaining input-to-output galvanic isolation
limited in voltage only by the insulation system of the
associated magnetic assembly. A ±2% internal bandgap
reference, internal operational amplifier, very high speed
comparator, and output buffer allow production of rugged,
high performance, high efficiency power supplies of 50W
or more, which can still be over 80% efficient at outputs
of 1.0W or less. The wide dynamic range of the controller
system allows designs with extremely wide line and load
variations with much less difficulty and much higher
efficiency than usual. The exceptionally wide input voltage
range also allows better usage of energy stored in input
dropout capacitors than with other PWM ICs. Remote on/
off controls allow either latching or nonlatching remote
shutdown. During shutdown, the power required is under
6.0mW.
For detailed circuit and application information, please
refer to application notes AN-H13, AN-H21 to AN-H24.
Functional Block Diagram
11 (14)
VREF
FB
15 (19)
COMP
14 (18)
Error
Amplifier
–
+
4V
REF
GEN
2V –
+
+
–
16 (20)
BIAS
7 (9)
VDD
1 (3)
+VIN
Current
Sources
To 1.2V
Internal
Circuits
–
–
8.1V
+
+ 8.6V
Pre-regulator/Startup
Note:
Pin numbers in parentheses are for PLCC package.
Doc.# DSFP-HV9120
C031314
OSC OSC
IN OUT
9 (11) 8 (10)
OSC
Modulator
Comparator
R
Q
S
Current Limit
Comparator
T
Undervoltage
Comparator
S
Q
R
Q To VDD
5 (6)
OUTPUT
6 (8)
-VIN
4 (5)
SENSE
VDD
12 (16)
SHUTDOWN
13 (17)
RESET
Supertex inc.
www.supertex.com
1 page  
Test Circuits
+10V
(VDD)
(FB)
Reference
GND
(-VIN)
0.1µF
Error Amp ZOUT
1.0V swept 100Hz - 2.2MHz
60.4k
–
+ Tektronix
P6021
(1 turn
40.2k
V1 secondary)
V2
0.1V swept 10Hz - 1.0MHz
PSRR
10.0V
4.0V
100k 1%
Reference
0.1µF
100k 1%
–
+
V2
Note:
Set feedback voltage so that VCOMP = VDIVIDE ± 1.0mV before connecting transformer.
HV9120
V1
Detailed Description
Pre regulator
The pre regulator/startup circuit for the HV9120 consists of
a high-voltage n-channel depletion-mode DMOS transistor
driven by an error amplifier to form a variable current path
between the VIN terminal and the VDD terminal. Maximum
current (about 20 mA) occurs when VDD = 0, with current re-
ducing as VDD rises. This path shuts off altogether when VDD
rises to somewhere between 7.8 and 9.4V, so that if VDD is
held at 10 or 12V by an external source (generally the sup-
ply the chip is controlling), no current other than leakage is
drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
CSTORAGE ≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable. A common resistor divider string
is used to monitor VDD for both the undervoltage lockout cir-
cuit and the shutoff circuit of the high voltage FET. Setting
the undervoltage sense point about 0.6V lower on the string
than the FET shutoff point guarantees that the undervoltage
lockout always releases before the FET shuts off.
Bias Circuit
An external bias resistor, connected between the bias pin
and VSS is required by the HV9120 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. Nominal external bias current requirement is 15 to
20µA, which can be set by a 390 to 510kΩ resistor if a 10V
VDD is used, or a 510 to 680kΩ resistor if VDD will be 12V. A
precision resistor is not required; ±5% is fine.
Clock Oscillator
The clock oscillator of the HV9120 consists of a ring of
CMOS inverters, timing capacitors, a capacitor discharge
FET, and a frequency dividing flip-flop. A single external re-
sistor between the OSC IN and OSC OUT pins is required
to set oscillator frequency (see graph).
One difference exists between the Supertex HV9120 and
competitive 9120s: The oscillator is shut off when a shutoff
command is received. This saves about 150µA of quiescent
current, which aids in the construction of power supplies
to meet CCITT specification I-430, and in other situations
where an absolute minimum of quiescent power dissipation
is required.
Reference
The Reference of the HV9120 consists of a stable bandgap
reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of
the reference buffer amplifier are trimmed during manufac-
ture so that the output of the error amplifier, when connected
in a gain of -1 configuration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplifier. As a con-
sequence, even though the observed reference voltage of a
specific part may not be exactly 4.0V, the feedback voltage
required for proper regulation will be.
A ≈ 50kΩ resistor is placed internally between the output
of the reference buffer amplifier and the circuitry it feeds
(reference output pin and non-inverting input to the error
amplifier). This allows overriding the internal reference with
a low-impedance voltage source ≤6.0V. Using an external
reference reinstates the input offset voltage of the error am-
plifier, and its effect of the exact value of feedback voltage
Doc.# DSFP-HV9120
C031314
Supertex inc.
5 www.supertex.com
5 Page 
20-Lead PLCC Package Outline (PJ)
.353x.353in body, .180in height (max), .050in pitch
.048/.042
x 45O
3
D
D1
1 20
.150max
.075max
Note 1
(Index Area)
18
E
E1
.056/.042
x 45O
HV9120
8
.020max
(3 Places)
Note 2
e
Top View
13
Vertical Side View
A
A1 A2
Horizontal Side View
View
B
Base .020min
Plane
Seating
Plane
b1
bR
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
Symbol
A A1 A2 b b1 D D1 E E1 e R
MIN .165 .090 .062 .013
Dimension
(inches)
NOM
.172
.105
-
-
MAX .180 .120 .083 .021
JEDEC Registration MS-018, Variation AA, Issue A, June, 1993.
Drawings not to scale.
Supertex Doc. #: DSPD-20PLCCPJ, Version C031111
.026
-
.032
.385
.390
.395
.350
.353
.356
.385 .350
.025
.390
.353
.050
BSC
.035
.395 .356
.045
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
Doc.# DSFP-HV9120
C031314
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
11 www.supertex.com
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HV9120.PDF ] | |
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