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PDF HV7620 Data sheet ( Hoja de datos )
| Número de pieza | HV7620 | |
| Descripción | 32-Channel Serial to Parallel Converter | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
HV7620
40MHz, 32-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
►► HVCMOS® technology
►► 5.0V logic and 12V supply rail
►► Output voltage up to +200V
►► Low power level shifting
►► Source/sink current minimum 50mA
►► 40MHz equivalent data rate
►► Latched data outputs
►► Forward and reverse shifting options (DIR pin)
►► Chip select
►► Polarity function
General Description
The HV7620 is a low-voltage serial to high-voltage parallel
converter with push-pull outputs. This device has been designed
for use as a driver for color AC plasma displays.
The device has 4 parallel 8-bit shift registers permitting data rates
four times the speed of one. The data is clocked in simultaneously
on all four data inputs with a single clock. Data is shifted in on a
low to high transition of the clock. The latches and control logic
perform the output enable function.
The DIR pin causes clockwise (CW) shifting of the data when
connected to VDD1, and counterclockwise (CCW) shifting when
connected to LVGND. Operation of the shift register is not affected
by the LE (latch enable) input. Transfer of data from the shift
registers to the latches occurs when the LE input is high. Data is
stored in the latches when LE is low. The current source on the
logic inputs provides active pull up when the input pins are open.
Functional Block Diagram
DINA
DOUTA
CLK
DINB
DOUTB
DIR
DINC
DOUTC
DIND
DOUTD
LE BLA CS
8-Bit
Shift
Register
8
QA1
8-Bit
Latches
QA8
≈≈
BLB
8-Bit
Shift
Register
8
QB1
8-Bit
Latches
QB8
≈≈
BLC
8-Bit
Shift
Register
8
QC1
8-Bit
Latches
QC8
≈≈
BLD
QD1
8-Bit
Shift
Register
8
8-Bit
Latches
QD8
≈≈
POL
≈
≈
≈
HVOUTA1
HVOUTB1
HVOUTC1
HVOUTD1
HVOUTA8
HVOUTB8
HVOUTC8
HVOUTD8
Doc.# DSFP-HV7620
C112213
Supertex inc.
www.supertex.com
1 page  
Function Table
Inputs
Function
DINA DINB DINC DIND CLK LE DIR BLA BLB BLC BLD CS POL
A
HV7620
HVOUT
BC
D
All O/P High X X X X X X X X X X X L L H H H H
All O/P Low X X X X X X X X X X X L H L L L L
“A”†
Outputs X X X X X X X L X X X X H L * * *
Low
Normal
Polarity
XXXXXXXHHHHHH
No Inversion
Outputs
Inverted
X
X
X
X
X
X
X
HHHHH
L
Inversion
Transparent
Mode
H
L
L
L
↑
H
X
HHHHHHHL
L
L
Data Stored X X X X X L X H H H H H H
Stored data
Shift CWA X
X
X
X
↑
H
H
H
H
H
H
H
X
AN BN CN DN
→→→→
AN+1 BN+1 CN+1 DN+1
Shift CCWB X
X
X
X
↑
H
L
H
H
H
H
H
AN BN CN DN
X →→→→
AN-1
BN-1
CN-1
DN-1
Notes:
H = High level, L = Low level, X = Irrelevant, ↑ = Low to high transition.
* = Dependent on previous stage’s state before the last CLK ↑ for last LE high.
† = BLB, BLC and BLD will have similar effect on their respective output.
Power-up sequence:
1. GND (HV, LV)
2. VDD1
3. VDD2
4. VPP
5. Logic Input Signals
To power down reverse the sequence above.
Doc.# DSFP-HV7620
C112213
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HV7620.PDF ] | |
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