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PDF HV7224 Data sheet ( Hoja de datos )
| Número de pieza | HV7224 | |
| Descripción | 40-Channel Symmetric Row Driver | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
HV7224
40-Channel
Symmetric Row Driver
Features
►►HVCMOS® technology
►►Symmetric row drive (reduces latent imaging in
ACTFEL displays)
►►Output voltage up to +240V
►►Low power level shifting
►►Source/sink current minimum 70mA
►►Shift register speed 3.0MHz
►►Pin-programmable shift direction (DIR, SHIFT)
General Description
The HV7224 is a low-voltage serial to high-voltage parallel
converter with push-pull outputs. It is especially suitable for use
as a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
When the data reset pin (DRIOA/DRIOB) is at logic high, it will reset
all the outputs of the internal shift register to zero. At the same
time, the output of the shift register will start shifting a logic high
from the least significant bit to the most significant bit. The DRIOA/
DRIOB can be triggered at any time. The DIR and SHIFT pins
control the direction of data shift through the device. When DIR is
at logic high, DRIOA is the input and DRIOB is the output. When DIR
is grounded, DRIOB is the input and the DRIOA is the output. See
the Output Sequence Operation Table for output sequence. The
POL and OE pins perform the polarity select and output enable
function respectively. Data is loaded on the low to high transition
of the clock. A logic high will cause the output to swing to VPP if
POL is high, or to GND if POL is low. All outputs will be in High-Z
state if OE is at logic high. Data output buffers are provided for
cascading devices.
Functional Block Diagram
VPP
OE
POL
VDD
DRIOA
Level
Translator
P
HVOUT1
N
SHIFT
CLK
DIR
S/R
Level
Translator
P
HVOUT2
N
Doc.# DSFP-HV7224
C072413
DRIOB
GND
Level
Translator
P
HVOUT40
N
Supertex inc.
www.supertex.com
1 page  
Function Table
I/O Relations
CLK
Inputs
DIR S/R DATA
O/P HIGH
X
X
H
O/P OFF
X
X
L
O/P LOW
X
X
H
O/P OFF
X
X
X
Notes:
H = logic high level, L = logic low level, X = irrelevant
Data
Only
oinnpeuta(cDtivReIOo) ulotpaudtecdaonnbteheselot wat-tao-thimigeh.
transition
of
the
clock.
POL
H
X
L
X
OE
L
L
L
H
HV7224
HV Outputs
H
HIGH-Z
L
All O/P HIGH-Z
Output Sequence Operation Table
DIR
SHIFT
Data Reset In
LL
DRIOB
HL
DRIOA
LH
DRIOB
HH
DRIOA
Notes:
* Reference to package outline or chip layout drawing.
1.
2.
DDRRIIOOAB
is
is
DDRRIIOOBA
delayed
delayed
by
by
40
40
clock
clock
pulses.
pulses.
Data Reset Out
DRIOA1
DRIOB2
DRIOA1
DRIOB2
HVOUT # Sequence
40 → 1
1 → 40
20 → 1 → 40 → 21
21 → 40 → 1 → 20
Direction*
Doc.# DSFP-HV7224
C072413
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HV7224.PDF ] | |
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