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PDF HV623PG Data sheet ( Hoja de datos )
| Número de pieza | HV623PG | |
| Descripción | 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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HV623
32-Channel 128-Level Amplitude Gray-Shade
Display Column Driver
Ordering Information
Device
HV623
Package Option
64-Lead 3-sided Plastic Gullwing
HV623PG
Features
5V CMOS inputs
Up to 80V modulation voltage
Capable of 128 levels of gray shading
20MHz data throughput rate
32 outputs per device (can be cascaded)
Pin-programmable shift direction (DIR)
D/A conversion cycle time is 32µs
Diodes in output structure allow usage
in energy recovery systems
Integrated HVCMOS® technology
Available in 3-sided 64-lead gullwing package
Absolute Maximum Ratings
Supply voltage, VDD1
Supply voltage, VPP1
Logic input levels1
Ground current 2
Continuous total power dissipation3
-0.5V to +7.5V
-0.5V to +90V
-0.5 to VDD + 0.5V
1.5A
1W
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
-40°C to +70°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 70°C at 22.2mW/°C.
General Description
The HV623 is a 32-channel driver IC for gray shade display use.
It is designed to produce varying output voltages between 3 and
80 volts. This amplitude modulation at the output is facilitated by
an external ramp voltage VR. See Theory of Operation for detailed
explanation.
This device consists of a dual 16-bit shift registers, 32 data latches
and comparators, and control logic to preform 128 levels of gray
shading. There are 7 bits of data inputs. Data is shifted through the
shift registers at both edges of the clock, resulting a data transfer
rate of twice of the shift clock frequency. When the DIR pin is high,
CSI/CSO is the input/output for the chip select pulse. When DIR
is low, CSI/CSO is the output/input for the chip select pulse. The
DIR = HIGH also allows the HV623 to shift data in the counter-
clockwise direction when viewed from the top of the package.
When the DIR pin is low, data is shifted in the clockwise direction.
The output circuitry allows the energy which is stored in the output
capacitance to be returned to VPP through the body diode of the
output transistor.
12-122
1 page  
Output Stage Detail
VCTL
RCTL
VR
CH
VPP
Internal
Logic
&
Bias
Circuit
Q1
HVOUT
Q2
Test Circuit
High-voltage Analog Output Source Current (I )
AOH
For gray shade #1 (000 0000)
VR VPP = 80V
HV623
HV623
+–
70V
0V
Logic
LVGND
Output
Stage
HVGND
HVOUT
+
1KΩ Vtst
-
10KΩ
1. Set HVOUT = Low.
2. Apply VPP = 80V.
3. Apply a step voltage of 70V at VR (slew rate = 4.1V/µs).
4. Measure voltage across the 1KΩ resistor.
5.
Output
source
current
can
be
calculated
by
using
Vtst
1K
.
Functional Block Diagram
VCTL
RCTL
1
2
Dual
16-bit
Shift Registers
L/E Data
7 Latches and 7
Latches
Comparators
L/E Data
7 Latches and 7
Latches
Comparators
See Output Stage Detail
GND
VR VPP
RS
F/F
Output
Stage
HVOUT 1
RS
F/F
Output
Stage
HVOUT 2
DIR I/O
Buffers
31
32
SC
SC
I/O
Buffers
Shift
Clock
Buffer
L/E Data
Latches
L/E Data
Latches
Data In
Buffers
7 Latches and 7
Comparators
RS
F/F
Output
Stage
HVOUT 31
7 Latches and 7
Comparators
RS
F/F
Output
Stage
HVOUT 32
Clear
7
Count
Counter
CC
Load
Reset
Counter
Clear
Pulse
Generator
Load
Count
Buffer
Count
Clock
Buffer
CSI
CSO
SC D7
D1
LC CC
SC = Shift Clock
LC = Load Count
CC = Count Clock
CSI = Chip Select Input
CSO = Chip Select Output
*Strobe = twice the SC frequency
12-126
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HV623PG.PDF ] | |
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