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PDF HV62208PG Data sheet ( Hoja de datos )

Número de pieza HV62208PG
Descripción 32-Channel 256 Gray-Shade High Voltage Driver
Fabricantes Supertex Inc 
Logotipo Supertex  Inc Logotipo



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HV62208
32-Channel 256 Gray-Shade High Voltage Driver
Ordering Information
Device
HV62208
Package Option
64-Lead 3-Sided Plastic Gullwing
HV62208PG
Die
HV62208X
Features
HVCMOS® technology
5V CMOS inputs
Up to 80V output voltage
PWM gray shade conversion
Capable of 256 levels of gray shading
Balanced shift clock complies with RS-422
8MHz shift and count clock frequency
16MHz data throughput rate
8 bit data bus
32 outputs per device
BLANK function
Absolute Maximum Ratings
Supply voltage, VDD
Supply voltage, VPP
Supply voltage, VNN
Logic input levels
Continuous total power dissipation
Operating temperature range
Storage temperature range
-0.5V to +7.5V
-0.5V to +80V
-15V to 0V
-0.5 to VDD + 0.5V
1.2W
-40°C to +85°C
-65°C to +150°C
Notes:
All voltages are referenced to GND.
Maximum VPP to VNN voltage is 90V.
For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.
General Description
Not recommended for new designs. Please use HV632 instead.
The HV622 is a 32-channel gray-shade column driver IC de-
signed for driving electrofluorescent displays. Using Supertex’s
unique HVCMOS® technology, it is capable of 256 levels of gray
shading by PWM conversion.
The shift clock is a balanced clock with electrical characteristics
complying with EIA RS-422 standard. Input data, in groups of
eight, is latched into a set of data latches on both edges of the shift
clock. The data shifted in the first data latch corresponds to
HVOUT1, the second data latch corresponds to HVOUT2, and so on.
These data are compared to the contents of the master binary
counter which counts on both edges of the count clock. Each time
the master counter begins to decrement from 1111 1111, the data
in the data latches are compared with the contents of the counter;
if they match, the corresponding outputs will go high. The master
counter counts down to 0000 0001 and then starts to count up
again. The outputs that are at high will stay at high until the
contents of the counter match the data in the data latches again.
Therefore, the higher the binary data in the data latches, the
longer the outputs will stay at high. Thus, different high voltage
pulse widths are produced. When the counter reaches its
1111 1111 count while counting up, the device is ready for the
next operation cycle. A data value of 0000 0000 produces no
pulse; the output stays low.
The BLANK input signal will reset the master counter to all ones
(1111 1111) and set all high voltage outputs to low.
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex prod1ucts, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

1 page




HV62208PG pdf
Timing Diagrams
HV62208
t CW
CSI
Shift
Clock
t CSS
50%
50%
t CSH
SC1
LOADING LAST DEVICE
t SCC
SC2
SC16
Data
1–8
50%
DATA
SET 1
DATA
SET 2
t DSS
t DSH
DATA
SET 3
t DW
tLCW
Load
Count
Count
Clock
50%
50%
t LCD
50%
DATA DATA
SET 31 SET 32
t CCW
50%
50%
t CCD
90%
HVOUT
BLANK
HVOUT
t BLW
10%
50%
50%
t BLD
90%
NEXT LOADING CYCLE
SC1
DATA
SET 1
DATA
SET 2
SCN
DATA DATA
SET 2N -1 SET 2N
t CCC
50%
50%
t CCD
90%
10%
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VPP
VNN
VIH
VIL
VPP
VNN
Count
Clock
50%
3 21
255 254
t CDD
50%
1
2
3
VIH
VIL
5

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