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PDF HYB3164805TL-60 Data sheet ( Hoja de datos )
| Número de pieza | HYB3164805TL-60 | |
| Descripción | 8M x 8-Bit Dynamic RAM | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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8M x 8-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
HYB 3164805J/T(L) -50/-60
HYB 3165805J/T(L) -50/-60
Preliminary Information
• 8 388 608 words by 8-bit organization
• 0 to 70 ˚C operating temperature
• Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
• Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
• Single + 3.3 V (± 0.3V) power supply
• Low power dissipation
max. 396 active mW ( HYB 3164805J/T(L)-50)
max. 360 active mW ( HYB 3164805J/T(L)-60)
max. 504 active mW ( HYB 3165805J/T(L)-50)
max. 432 active mW ( HYB 3165805J/T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
• Hyper page mode (EDO) capability
• 8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164805J/T(L))
• 4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165805J/T(L))
• Plastic Package:
P-SOJ-34-1 500 mil HYB 3164(5)805J
P-TSOPII-34-1 500 mil HYB 3164(5)805T(L)
Semiconductor Group
149
1 page  
HYB3164(5)805J/T(L)-50/-60
8M x 8 EDO-DRAM
Block Diagram for HYB 3165805J/T(L)
Semiconductor Group
153
5 Page 
HYB3164(5)805J/T(L)-50/-60
8M x 8 EDO-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Parameter
Symbol
Limit Values
-50 -60
min. max. min. max.
CAS precharge to RAS Delay
OE pulse width
OE hold time from CAS high
WE pulse width to output disable at CAS
high
tRHCP
tOEP
tOEHC
tWPZ
27
7
7
7
–
–
–
–
35 –
10 –
10 –
10 –
Output buffer turn-off delay from WE tWPZ 0
10 0
10
Unit Note
ns
ns
ns
ns
ns
Hyper Page Mode (EDO) Read-
modify-Write Cycle
Hyper page mode (EDO) read-write
cycle time
CAS precharge to WE
tPRWC
51
tCPWD 41
–
–
66 –
49 –
ns
ns
CAS before RAS refresh cycle
CAS setup time
tCSR
5
–
5
–
CAS hold time
tCHR
8
–
10 –
RAS to CAS precharge time
tRPC
5
–
5
–
Write to RAS precharge time
tWRP
8
–
10 –
Write hold time referenced to RAS
tWRH
8
–
10 –
ns
ns
ns
ns
ns
CAS-before-RAS counter test cycle
CAS precharge time (CAS-before-RAS tCPT 35 –
counter test cycle)
40 –
ns
Self Refresh Cycle
RAS pulse width during self refresh
RAS precharge time during self refresh
CAS hold time during self refresh
tRASS
tRPS
tCHS
100k
84
-50
_
_
_
100k
104
-50
_
_
_
ns 17
ns 17
ns 17
Semiconductor Group
159
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet HYB3164805TL-60.PDF ] | |
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| HYB3164805TL-60 | 8M x 8-Bit Dynamic RAM | Siemens Semiconductor Group |
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