PDF HYB3164165BT-60 Data sheet ( Hoja de datos )

Número de pieza	HYB3164165BT-60
Descripción	4M x 16-Bit Dynamic RAM
Fabricantes	Siemens Semiconductor Group
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No Preview Available ! 4M x 16-Bit Dynamic RAM (8k, 4k & 2k Refresh, EDO-version) Preliminary Information HYB 3164165BT(L) -40/-50/-60 HYB 3165165BT(L) -40/-50/-60 HYB 3166165BT(L) -40/-50/-60 • 4 194 304 words by 16-bit organization • 0 to 70 °C operating temperature • Hyper Page Mode - EDO - operation • Performance: -40 -50 -60 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/write cycle time Hyper page mode (EDO) cycle time 40 10 20 69 16 50 60 ns 13 15 ns 25 30 ns 84 104 ns 20 25 ns • Single + 3.3 V (± 0.3V) power supply • Low power dissipation: -40 -50 -60 HYB3166165BT(L) 864 702 558 mW HYB3165165BT(L) 486 396 324 mW HYB3164165BT(L) 306 252 216 mW 7.2 mW standby (TTL) 3.6 mW standby (MOS) 720 µA standby for L-version • Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and Self Refresh (L-version only • 2 CAS / 1 WE byte control • 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165BT) 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165BT) 2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165BT) • 128 ms refresh period for L-versions • Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 12.97 1 page HYB3164(5/6)165BT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE .UCAS .LCAS & No. 2 Clock Generator Data in Buffer 16 Data out Buffer 16 OE Column 9 Address A0 Buffer(9) A1 9 Column Decoder A2 A3 Refresh A4 Controller A5 Sense Amplifier I/O Gating 16 A6 A7 Refresh A8 Counter (13) A9 A10 13 512 x16 A11 Row Row Memory Array A12 13 Address Buffers(13) 13 Decoder 8192 8192x512x16 RAS No. 1 Clock Generator Block Diagram for HYB 3164165BT(L) Semiconductor Group 5 5 Page HYB3164(5/6)165BT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns AC64-2E Parameter Symbol - 40 Limit Values - 50 - 60 Unit Note min. max. min. max. min. max. Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay tCLZ tOFF tOEZ tDZC tDZO tCDD tODD 0 – 0 – 0 – ns 8 0 10 0 13 0 15 ns 12 0 10 0 13 0 15 ns 12 0 – 0 – 0 – ns 13 0 – 0 – 0 – ns 13 10 – 13 – 15 – ns 14 10 – 13 – 15 – ns 14 Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 5 – 7 – 10 – ns 5 – 7 – 10 – ns 0 – 0 – 0 – ns 15 6 – 8 – 10 – ns 6 – 8 – 10 – ns 0 – 0 – 0 – ns 16 5 – 7 – 10 – ns 16 Read-modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 89 – 109 – 133 – ns 52 – 65 – 77 – ns 15 22 – 28 – 32 – ns 15 32 – 40 – 47 – ns 15 5 – 7 – 10 – ns Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time Access time from CAS precharge Output data hold time tHPC tCPA tCOH 16 – 20 – 24 – ns – 22 – 27 – 32 ns 7 3 – 5 – 5 – ns Semiconductor Group 11 11 Page

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