PDF HYB3164165ATL-60 Data sheet ( Hoja de datos )

Número de pieza	HYB3164165ATL-60
Descripción	4M x 16-Bit Dynamic RAM
Fabricantes	Siemens Semiconductor Group
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No Preview Available ! 4M x 16-Bit Dynamic RAM (8k, 4k & 2k Refresh, EDO-Version) Advanced Information HYB 3164165AT(L) -40/-50/-60 HYB 3165165AT(L) -40/-50/-60 HYB 3166165AT(L) -40/-50/-60 • 4 194 304 words by 16-bit organization • 0 to 70 °C operating temperature • Hyper Page Mode - EDO - operation • Performance: -40 -50 -60 tRAC RAS access time 40 50 60 ns tCAC CAS access time 10 13 15 ns tAA Access time from address 20 25 30 ns tRC Read/write cycle time 69 84 104 ns tHPC Hyper page mode (EDO) 16 20 25 ns cycle time • Single + 3.3 V (± 0.3V) power supply • Low power dissipation: -40 HYB3166165AT(L) 1008 HYB3165165AT(L) 756 HYB3164165AT(L) 612 -50 612 504 324 -60 450 mW 360 mW 324 mW 7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 µA standby for L-version • Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and Self Refresh (L-version only • 2 CAS / 1 WE byte control • 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT) 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT) 2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT) • 256ms refresh period for L-versions • Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 6.97 1 page HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE .UCAS .LCAS & No. 2 Clock Generator Data in Buffer 16 Data out Buffer 16 OE Column 9 Address A0 Buffer(9) A1 9 Column Decoder A2 A3 Refresh A4 Controller A5 Sense Amplifier I/O Gating 16 A6 A7 Refresh A8 Counter (13) A9 A10 13 512 x16 A11 Row Row Memory Array A12 13 Address Buffers(13) 13 Decoder 8192 8192x512x16 RAS No. 1 Clock Generator Block Diagram for HYB 3164165AT(L) Semiconductor Group 5 5 Page HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns AC64-2E Parameter Symbol Limit Values Unit Note - 40 - 50 - 60 min. max. min. max. min. max. Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay tCLZ tOFF tOEZ tDZC tDZO tCDD tODD 0 – 0 – 0 – ns 8 0 10 0 13 0 15 ns 12 0 10 0 13 0 15 ns 12 0 – 0 – 0 – ns 13 0 – 0 – 0 – ns 13 10 – 13 – 15 – ns 14 10 – 13 – 15 – ns 14 Write Cycle Write command hold time tWCH 5 – 7 – 10 – ns Write command pulse width tWP 5 – 7 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns 15 Write command to RAS lead time tRWL 6 – 8 – 10 – ns Write command to CAS lead time tCWL 6 – 8 – 10 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 5 – 7 – 10 – ns 16 Read-modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tA WD tOEH 89 – 52 – 22 – 32 – 5– 109 – 65 – 28 – 40 – 7– 133 – 77 – 32 – 47 – 10 – ns ns 15 ns 15 ns 15 ns Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time Access time from CAS precharge Output data hold time tHPC tCPA tCOH 16 – 20 – 24 – ns – 22 – 27 – 32 ns 7 3 – 5 – 5 – ns Semiconductor Group 11 11 Page

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