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PDF HYB314175BJ-50 Data sheet ( Hoja de datos )
| Número de pieza | HYB314175BJ-50 | |
| Descripción | 3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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3.3V 256 K x 16-Bit EDO-DRAM
3.3V 256 K x 16-Bit EDO-DRAM
(Low power version with Self Refresh)
HYB 314175BJ-50/-55/-60
HYB 314175BJL-50/-55/-60
Preliminary Information
• 262 144 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast access and cycle time
• RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)
• CAS access time:
13ns (-50 & -55 version)
15 ns (-60 version)
• Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)
• Hype page mode (EDO) cycle time
20 ns (-50 & -55 version)
25 ns (-60 version)
• High data rate
50 MHz (-50 & -55 version)
40 MHz (-60 version)
• Single + 3.3 V (±0.3 V) supply with a built-
in VBB generator
• Low Power dissipation
max. 450 mW active (-50 version)
max. 432 mW active (-55 version)
max. 378 mW active (-60 version)
• Standby power dissipation
7.2 mW standby (TTL)
3.6 mW max. standby (CMOS)
0.72 mW max. standby (CMOS) for
Low Power Version
• Output unlatched at cycle end allows two-
dimensional chip selection
• Read, write, read-modify write, CAS-
before-RAS refresh, RAS-only refresh,
hidden-refresh and hyper page (EDO)
mode capability
• 2 CAS / 1 WE control
• Self Refresh (L-Version)
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms
• 512 refresh cycles / 128 ms
Low Power Version only
• Plastic Packages:
P-SOJ-40-1 400mil width
The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide
P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with
commonly used automatic testing and insertion equipment. System oriented features include Self
Refresh (L-Version), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance
logic device families.
Semiconductor Group
1
7.96
1 page  
HYB 314175BJ/BJL-50/-55/-60
3.3V 256K x 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70 °C
Storage temperature range..................................................................................... – 55 to + 150 °C
Input/output voltage ..................................................................................... – 1 to (VCC + 0.5, 4.6) V
Power supply voltage................................................................................................... – 1 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
min.
max.
Input high voltage
VIH
Input low voltage
VIL
LVTTL Output high voltage (IOUT = – 2.0 mA)
VOH
LVTTL Output low voltage (IOUT = 2 mA)
VOL
LVCMOS Output high voltage (IOUT = – 100 µA) VOH
LVCMOS Output low voltage (IOUT = 100 µA)
VOL
Input leakage current, any input
(0 V < VIN < 7 V, all other inputs = 0 V)
II(L)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC)
IO(L)
Average VCC supply current:
ICC1
-50 version
-55 version
-60 version
2.4
– 1.0
2.4
–
2.4
–
– 10
– 10
–
VCC + 0.5
0.8
–
0.4
–
0.4
10
10
125
120
105
Unit Notes
V1
V1
V1
V1
V1
V1
µA 1
µA 1
mA 2, 3, 4
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
Average VCC supply current during
RAS-only refresh cycles:
ICC2
ICC3
-50 version
-55 version
-60 version
–
–
2 mA –
125 mA 2, 4
120
105
Semiconductor Group
5
5 Page 
HYB 314175BJ/BJL-50/-55/-60
3.3V 256K x 16 EDO-DRAM
Read Cycle
Semiconductor Group
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet HYB314175BJ-50.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HYB314175BJ-50 | 3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh | Siemens Semiconductor Group |
| HYB314175BJ-50- | 3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh | Siemens Semiconductor Group |
| HYB314175BJ-55 | 3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM Low power version with Self Refresh | Siemens Semiconductor Group |
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