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PDF HYB3117805BSJ-50- Data sheet ( Hoja de datos )
| Número de pieza | HYB3117805BSJ-50- | |
| Descripción | 2M x 8 - Bit Dynamic RAM 2k Refresh | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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2M x 8 - Bit Dynamic RAM
2k Refresh
(Hyper Page Mode- EDO)
HYB3117805BSJ -50/-60/-70
Advanced Information
• 2 097 152 words by 8-bit organization
• 0 to 70 °C operating temperature
• Performance:
tRAC
tCAC
tAA
tRC
tHPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Hyper page mode (EDO)
cycle time
-50 -60 -70
50 60 70 ns
13 15 20 ns
25 30 35 ns
84 104 124 ns
20 25 30 ns
• Single + 3.3 V (± 0.3 V) supply
• Low power dissipation
max. 432 mW active (-50 version)
max. 396 mW active (-60 version)
max. 360 mW active (-70 version)
7.2 mW standby (LV-TTL)
3.6 mW standby (CMOS)
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
• Hyper page mode (EDO) capability
• All inputs, outputs and clocks fully TTL-compatible
• 2048 refresh cycles / 32 ms (2k-Refresh)
• Plastic Package:
P-SOJ-28-3 400 mil
Semiconductor Group
1
1.96
1 page  
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage...................................................................................................-1.0V to 4.6 V
Power dissipation..................................................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
min.
max.
Input high voltage
Input low voltage
TTL Output high voltage (IOUT = – 2 mA)
TTL Output low voltage (IOUT = 2 mA)
CMOS Output high voltage (IOUT = –100 uA)
CMOS Output low voltage (IOUT = 100 uA)
Input leakage current
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
Average VCC supply current:
-50 ns version
-60 ns version
-70 ns version
VIH
VIL
VOH
VOL
VOH
VOL
II(L)
IO(L)
ICC1
2.0 Vcc+0.5
– 0.5 0.8
2.4 –
– 0.4
VCC-0.2 –
– 0.2
– 10 10
– 10 10
– 120
– 110
– 100
Unit Test
Condition
V 1)
V 1)
V 1)
V 1)
V
V
µA 1)
µA 1)
mA 2) 3) 4)
mA 2) 3) 4)
mA 2) 3) 4)
(RAS, CAS, address cycling, tRC = tRC min.)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only ICC3
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
–
–
–
–
2 mA –
120 mA 2) 4)
110 mA 2) 4)
100 mA 2) 4)
(RAS cycling: CAS = VIH, tRC = tRC min.)
Semiconductor Group
5
5 Page 
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
RAS
V
IH
VIL
CAS
V
IH
VIL
V
IH
Address
VIL
V
IH
WE
VIL
V
IH
OE
VIL
V
I/O IH
(Inputs) VIL
V
I/O OH
(Outputs) VOL
tRC
tRAS
tRP
tCSH
tRCD
tRSH
tCAS
tASR
tRAD
tASC
tCAH
tRAL
Row
Column
tRAH
tRCS
tAA
tOEA
tCRP
tASR
tRCH
tRRH
Row
tDZC
tDZO
tCAC
tCLZ
Hi Z
tRAC
tODD
tCDD
tOEZ
tOFF
Valid Data Out
Hi Z
“H” or “L”
WL1
Read Cycle
Semiconductor Group
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet HYB3117805BSJ-50-.PDF ] | |
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