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PDF HYB3116160BST-70 Data sheet ( Hoja de datos )
| Número de pieza | HYB3116160BST-70 | |
| Descripción | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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1M x 16-Bit Dynamic RAM
(1k & 4k -Refresh)
HYB3116160BSJ/BST(L)-50/-60/-70
HYB3118160BSJ/BST(L)-50/-60/-70
Advanced Information
• 1 048 576 words by 16-bit organization
• 0 to 70 °C operating temperature
• Performance:
tRAC
tCAC
tAA
tRC
tPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
-50 -60 -70
50 60 70 ns
13 15 20 ns
25 30 35 ns
90 110 130 ns
35 40 45 ns
• Single + 3.3 V (± 0.3 V) supply
• Low power dissipation
max. 720 active mW ( HYB3118160BSJ/BST-50)
max. 648 active mW ( HYB3118160BSJ/BST-60)
max. 576 active mW ( HYB3118160BSJ/BST-70)
max. 360 active mW ( HYB3116160BSJ/BST-50)
max. 324 active mW ( HYB3116160BSJ/BST-60)
max. 288 active mW ( HYB3116160BSJ/BST-70)
7.2 mW standby (LV-TTL)
3.6 mW standby (LV-CMOS)
720 µW standby for L-version
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh
• Fast page mode capability
• 2 CAS / 1 WE
• All inputs, outputs and clocks fully LV-TTL-compatible
• 1024 refresh cycles / 16 ms for HYB 3118160BSJ
• 4096 refresh cycles / 64 ms for HYB 3116160BSJ
• Plastic Package:
P-SOJ-42-1 400 mil
P-TSOPII-50/44-1 400mil
Semiconductor Group
1
1.96
1 page  
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
I/O1 I/O2
I/O16
WE
.UCAS
.LCAS
&
No. 2 Clock
Generator
Data in
Buffer
16
Data out
Buffer
16
OE
Column
10 Address
A0 Buffer(10)
A1
A2
A3 Refresh
A4 Controller
A5
A6
A7 Refresh
A8 Counter (10)
A9
10
10 Column
Decoder
Sense Amplifier
I/O Gating
16
1024
x16
Row
10 Address
Buffers(10)
Row
Memory Array
10 Decoder 1024 1024x1024x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3118160BSJ
Semiconductor Group
5
5 Page 
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA).
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13)Either tDZC or tDZO must be satisfied.
14)Either tCDD or tODD must be satisfied.
15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of
the I/O pins (at access time) is indeterminate.
16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
Semiconductor Group
11
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet HYB3116160BST-70.PDF ] | |
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