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PDF ADG738 Data sheet ( Hoja de datos )

Número de pieza ADG738
Descripción CMOS/ Low-Voltage/ 3-Wire Serially-Controlled/ Matrix Switches
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! ADG738 Hoja de datos, Descripción, Manual

a
FEATURES
3-Wire Serial Interface
2.7 V to 5.5 V Single Supply
2.5 On Resistance
0.75 On-Resistance Flatness
100 pA Leakage Currents
Single 8-to-1 Multiplexer ADG738
Dual 4-to-1 Multiplexer ADG739
Power-On Reset
TTL/CMOS-Compatible
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
CMOS, Low-Voltage, 3-Wire
Serially-Controlled, Matrix Switches
ADG738 /ADG739
FUNCTIONAL BLOCK DIAGRAMS
ADG738
ADG739
S1 S1A
DA
S4A
D
S1B
DB
S8 S4B
INPUT SHIFT
REGISTER
DOUT
INPUT SHIFT
REGISTER
DOUT
SCLK DIN SYNC RESET
SCLK DIN SYNC
GENERAL DESCRIPTION
The ADG738 and ADG739 are CMOS analog matrix switches
with a serially-controlled 3-wire interface. The ADG738 is an
8-channel matrix switch, while the ADG739 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range.
The ADG738 and ADG739 utilize a 3-wire serial interface that
is compatible with SPI™, QSPI™, MICROWIRE™, and some
DSP interface standards. The output of the shift register DOUT
enables a number of these parts to be daisy-chained. On power-up,
the internal shift register contains all zeros and all switches
are in the OFF state.
Each switch conducts equally well in both directions when on,
making these parts suitable for both multiplexing and demulti-
plexing applications. As each switch is turned on or off by a
separate bit, these parts can also be configured as a type of switch
array, where any, all, or none of the eight switches may be closed
at any time. The input signal range extends to the supply rails.
All channels exhibit break-before-make switching action,
preventing momentary shorting when switching channels.
The ADG738 and ADG739 are available in 16-lead TSSOP
packages.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
2. Single Supply Operation. The ADG738 and ADG739 are
fully specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance, 2.5 typical.
4. Any configuration of switches may be on or off at any one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-lead TSSOP Package.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 page




ADG738 pdf
ADG738/ADG739
PIN FUNCTION DESCRIPTIONS
ADG738
1
2
3
4, 5, 6, 7
8
9, 10, 11, 12
13
14
15
16
ADG739
1
Mnemonic
SCLK
RESET
3 DIN
4, 5, 6, 7
8, 9
10, 11, 12, 13
14
15
16
Sxx
Dx
Sxx
VDD
GND
DOUT
2 SYNC
Function
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. These devices can accommodate serial input rates of up to 30 MHz.
Active low control input that clears the input register and turns all switches to the OFF
condition.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the
serial clock input.
Source. May be an input or output.
Drain. May be an input or output.
Source. May be an input or output.
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
Ground Reference.
Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of
the input shift register on the rising edge of SCLK. This is an open drain output which
should be pulled to the supply with an external resistor.
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift
register is enabled. Data is transferred on the falling edges of the following clocks.
Taking SYNC high updates the switch conditions.
PIN CONFIGURATIONS
SCLK 1
RESET 2
DIN 3
S1 4
S2 5
S3 6
S4 7
D8
ADG738
TOP VIEW
(Not to Scale)
16 SYNC SCLK 1
15 DOUT SYNC 2
14 GND DIN 3
13 VDD
S1A 4
12 S5
S2A 5
11 S6
S3A 6
10 S7
S4A 7
9 S8
DA 8
ADG739
TOP VIEW
(Not to Scale)
16 DOUT
15 GND
14 VDD
13 S1B
12 S2B
11 S3B
10 S4B
9 DB
Model
ADG738BRU
ADG739BRU
Temperature Range
–40°C to +85°C
–40°C to +85°C
ORDERING GUIDE
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Package Option
RU-16
RU-16
REV. 0
–5–

5 Page





ADG738 arduino
IDS
V1
SD
VS
RON = V1/IDS
Test Circuit 1. On Resistance
TEST CIRCUITS
ADG738/ADG739
IS (OFF)
A
VS
VD
S1
S2
S8
VDD
VDD
GND
D
Test Circuit 3. IS (OFF)
S1
S2
S8
VS
VDD
VDD
GND
ID (OFF)
DA
VD
Test Circuit 2. ID (OFF)
S1
S8
VS
VDD
VDD
GND
ID (ON)
DA
VD
Test Circuit 4. ID (ON)
VDD
VDD
ADG738*
S1
S2 THRU S7
S8
GND
D
VS1
VS8
RL
300
VOUT
CL
35pF
SYNC
VS1
VOUT
50%
50%
SYNC
90%
90%
VS1 = VS8
VOUT
* SIMILAR CONNECTION FOR ADG739
tOFF
tON
Test Circuit 5. Switching Times and Break-Before-Make Times
80%
80%
tOPEN
REV. 0
VDD
ADG738*
RS S
D
VS INPUT LOGIC
GND
SYNC
CL
1nF
VOUT
SWITCH OFF
SWITCH ON
QINJ = CL x VOUT
VOUT
* SIMILAR CONNECTION FOR ADG739
Test Circuit 6. Charge Injection
–11–

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