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PDF ADG731 Data sheet ( Hoja de datos )
| Número de pieza | ADG731 | |
| Descripción | 16-/32- Channel/ Serially Controlled 4 1.8 V to 5.5 V/ 2.5 V/ Analog Multiplexers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADG731 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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PRELIMINARY TECHNICAL DATA
= 16-/32- Channel, Serially Controlled 4 Ω
1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers
Preliminary Technical Data
ADG725/ADG731
FEATURES
3-Wire SPI Serial Interface
1.8 V to 5.5 V Single Supply
±2.5 V Dual Supply Operation
4 Ω On Resistance
0.5 Ω On Resistance Flatness
7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
Rail to Rail Operation
Power On Reset
Fast Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent devices with Parallel Interface
See ADG726/ADG732
S1
S32
FUNCTIONAL BLOCK DIAGRAMS
ADG731
INPUT SHIFT
REGISTER
S1A
S16A
D
S1B
S16B
ADG725
INPUT SHIFT
REGISTER
DA
DB
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
Battery Powered Systems
Medical Instrumentation
Automatic Test Equipment
GENERAL DESCRIPTION
The ADG725/ADG731 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers with a
serially controlled 3-wire interface. The ADG732 switches
one of thirty-two inputs (S1-S32) to a common output, D.
The ADG725 can be configured as a dual mux switching
one of sixteen inputs to one output or a differential mux
switching one of sixteen inputs to a differential output.
These mulitplexers utilize a 3-wire serial interface that is
compatible with SPITM, QSPITM, MICROWIRETM and
some DSP interface standards. On power-up, the internal
shift register contains all zeros and all switch are in the
OFF state.
These multiplexers are designed on an enhanced submi-
cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and ±2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
SCLK DIN SYNC
SCLK DIN SYNC
and have an input signal range which extends to the sup-
plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
They are available in either 48 lead CSP or TQFP
package.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
2. +1.8 V to +5.5 V Single or ±2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V ±10%, +3 V ±10% single supply and
±2.5 V ±10% dual supply rails.
3. On Resistance of 4 Ω.
4. Guaranteed Break-Before-Make Switching Action.
5. 7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
REV. PrD May 2002
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
1 page  
PRELIMINARY TECHNICAL DATA
TIMINGCHARACTERISTICS1,2
ADG725/ADG731
Parameter
Limit at TMIN, TMAX
Units
Conditions/Comments
t1 33
t2 13
t3 13
t4 13
t5 40
t6 5
t7 4.5
t8 33
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle time
SCLK High Time
SCLK Low Time
SYNC to SCLK falling edge setup time
Minimum SYNC low time
Data Setup Time
Data Hold Time
Minimum SYNC high time
NOTES
1See Figure 1.
2All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
SCLK
SYNC
DIN
t8 t4
t5
t7
t6
DB7
t1
t2 t3
DB0
Figure 1. 3-Wire Serial Interface Timing Diagram.
DB7 (MSB)
EN CSA CSB X
DB0 (LSB)
A3 A2 A1 A0
DATA BITS
DB7 (MSB)
EN CS
DB0 (LSB)
X A4 A3 A2 A1 A0
DATA BITS
Figure 2. ADG725 Input Shift Register Contents
Figure 3. ADG731 Input Shift Register Contents
REV. PrD
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TBD
TBD
TBD
TPC 10. Leakage Currents vs.
Temperature
TPC 13. TON/TOFF Times vs.
Temperature
TPC 16. On Response vs. Frequency
TBD
TBD
TPC 11. Supply Currents vs. Input
Switching Frequency
TPC 14. Off Isolation vs. Frequency
TBD
TBD
TPC 12. Charge Injection vs. Source
Voltage
TPC 15. Crosstalk vs. Frequency
REV. PrD
–11–
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ADG731.PDF ] | |
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